mirror of
https://github.com/golang/go.git
synced 2025-12-28 06:34:04 +00:00
all: REVERSE MERGE dev.simd (9ac524a) into master
This commit is a REVERSE MERGE. It merges dev.simd back into its parent branch, master. Merge List: + 2025-12-039ac524ab70[dev.simd] all: merge master (5945fc0) into dev.simd + 2025-12-038b41e841be[dev.simd] internal/buildcfg: default-disable simd experiment, for merge w/ master + 2025-12-03608dba4308[dev.simd] simd: make "best" instruction choice also depend on commutativity + 2025-11-25f3a306527c[dev.simd] simd, cmd/compile: add float -> float conversions + 2025-11-25d6564ed088[dev.simd] simd, cmd/compile: add int -> fp conversions + 2025-11-2586cd9b5c90[dev.simd] simd, cmd/compile: add float -> int conversions + 2025-11-241265ebfe27[dev.simd] internal/buildcfg: turn GOEXPERIMENT=simd back on Change-Id: I05a1eedc406ba6e7668ff2101917a0adef656452
This commit is contained in:
David Chase
commit
2b62144069
@ -42,12 +42,55 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
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ssa.OpAMD64VPBROADCASTW512,
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ssa.OpAMD64VPBROADCASTD512,
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ssa.OpAMD64VPBROADCASTQ512,
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ssa.OpAMD64VCVTPD2PSX128,
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ssa.OpAMD64VCVTPD2PSY128,
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||||
ssa.OpAMD64VCVTPD2PS256,
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ssa.OpAMD64VCVTDQ2PS128,
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ssa.OpAMD64VCVTDQ2PS256,
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ssa.OpAMD64VCVTDQ2PS512,
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ssa.OpAMD64VCVTQQ2PSX128,
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ssa.OpAMD64VCVTQQ2PSY128,
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ssa.OpAMD64VCVTQQ2PS256,
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ssa.OpAMD64VCVTUDQ2PS128,
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ssa.OpAMD64VCVTUDQ2PS256,
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ssa.OpAMD64VCVTUDQ2PS512,
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ssa.OpAMD64VCVTUQQ2PSX128,
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ssa.OpAMD64VCVTUQQ2PSY128,
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ssa.OpAMD64VCVTUQQ2PS256,
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ssa.OpAMD64VCVTPS2PD256,
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ssa.OpAMD64VCVTPS2PD512,
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ssa.OpAMD64VCVTDQ2PD256,
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ssa.OpAMD64VCVTDQ2PD512,
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ssa.OpAMD64VCVTQQ2PD128,
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ssa.OpAMD64VCVTQQ2PD256,
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ssa.OpAMD64VCVTQQ2PD512,
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ssa.OpAMD64VCVTUDQ2PD256,
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ssa.OpAMD64VCVTUDQ2PD512,
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ssa.OpAMD64VCVTUQQ2PD128,
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ssa.OpAMD64VCVTUQQ2PD256,
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ssa.OpAMD64VCVTUQQ2PD512,
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ssa.OpAMD64VCVTTPS2DQ128,
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ssa.OpAMD64VCVTTPS2DQ256,
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ssa.OpAMD64VCVTTPS2DQ512,
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ssa.OpAMD64VCVTPS2UDQ128,
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ssa.OpAMD64VCVTPS2UDQ256,
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ssa.OpAMD64VCVTPS2UDQ512,
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ssa.OpAMD64VCVTTPD2DQX128,
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ssa.OpAMD64VCVTTPD2DQY128,
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ssa.OpAMD64VCVTTPD2DQ256,
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ssa.OpAMD64VCVTTPS2QQ256,
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ssa.OpAMD64VCVTTPS2QQ512,
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ssa.OpAMD64VCVTTPD2QQ128,
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ssa.OpAMD64VCVTTPD2QQ256,
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ssa.OpAMD64VCVTTPD2QQ512,
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ssa.OpAMD64VCVTTPS2UDQ128,
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ssa.OpAMD64VCVTTPS2UDQ256,
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ssa.OpAMD64VCVTTPS2UDQ512,
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ssa.OpAMD64VCVTTPD2UDQX128,
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ssa.OpAMD64VCVTTPD2UDQY128,
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ssa.OpAMD64VCVTTPD2UDQ256,
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ssa.OpAMD64VCVTTPS2UQQ256,
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ssa.OpAMD64VCVTTPS2UQQ512,
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ssa.OpAMD64VCVTTPD2UQQ128,
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ssa.OpAMD64VCVTTPD2UQQ256,
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ssa.OpAMD64VCVTTPD2UQQ512,
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ssa.OpAMD64VPMOVSXBQ128,
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ssa.OpAMD64VPMOVSXWQ128,
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ssa.OpAMD64VPMOVSXDQ128,
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@ -816,12 +859,55 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
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ssa.OpAMD64VPCOMPRESSQMasked128,
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ssa.OpAMD64VPCOMPRESSQMasked256,
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ssa.OpAMD64VPCOMPRESSQMasked512,
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ssa.OpAMD64VCVTPD2PSXMasked128,
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ssa.OpAMD64VCVTPD2PSYMasked128,
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ssa.OpAMD64VCVTPD2PSMasked256,
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ssa.OpAMD64VCVTDQ2PSMasked128,
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ssa.OpAMD64VCVTDQ2PSMasked256,
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ssa.OpAMD64VCVTDQ2PSMasked512,
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ssa.OpAMD64VCVTQQ2PSXMasked128,
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ssa.OpAMD64VCVTQQ2PSYMasked128,
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ssa.OpAMD64VCVTQQ2PSMasked256,
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ssa.OpAMD64VCVTUDQ2PSMasked128,
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ssa.OpAMD64VCVTUDQ2PSMasked256,
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ssa.OpAMD64VCVTUDQ2PSMasked512,
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ssa.OpAMD64VCVTUQQ2PSXMasked128,
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ssa.OpAMD64VCVTUQQ2PSYMasked128,
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ssa.OpAMD64VCVTUQQ2PSMasked256,
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ssa.OpAMD64VCVTPS2PDMasked256,
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ssa.OpAMD64VCVTPS2PDMasked512,
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ssa.OpAMD64VCVTDQ2PDMasked256,
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ssa.OpAMD64VCVTDQ2PDMasked512,
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ssa.OpAMD64VCVTQQ2PDMasked128,
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ssa.OpAMD64VCVTQQ2PDMasked256,
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ssa.OpAMD64VCVTQQ2PDMasked512,
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ssa.OpAMD64VCVTUDQ2PDMasked256,
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ssa.OpAMD64VCVTUDQ2PDMasked512,
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ssa.OpAMD64VCVTUQQ2PDMasked128,
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ssa.OpAMD64VCVTUQQ2PDMasked256,
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ssa.OpAMD64VCVTUQQ2PDMasked512,
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ssa.OpAMD64VCVTTPS2DQMasked128,
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ssa.OpAMD64VCVTTPS2DQMasked256,
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ssa.OpAMD64VCVTTPS2DQMasked512,
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ssa.OpAMD64VCVTPS2UDQMasked128,
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ssa.OpAMD64VCVTPS2UDQMasked256,
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ssa.OpAMD64VCVTPS2UDQMasked512,
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ssa.OpAMD64VCVTTPD2DQXMasked128,
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ssa.OpAMD64VCVTTPD2DQYMasked128,
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ssa.OpAMD64VCVTTPD2DQMasked256,
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ssa.OpAMD64VCVTTPS2QQMasked256,
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ssa.OpAMD64VCVTTPS2QQMasked512,
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ssa.OpAMD64VCVTTPD2QQMasked128,
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ssa.OpAMD64VCVTTPD2QQMasked256,
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ssa.OpAMD64VCVTTPD2QQMasked512,
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ssa.OpAMD64VCVTTPS2UDQMasked128,
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ssa.OpAMD64VCVTTPS2UDQMasked256,
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ssa.OpAMD64VCVTTPS2UDQMasked512,
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ssa.OpAMD64VCVTTPD2UDQXMasked128,
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ssa.OpAMD64VCVTTPD2UDQYMasked128,
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ssa.OpAMD64VCVTTPD2UDQMasked256,
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ssa.OpAMD64VCVTTPS2UQQMasked256,
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ssa.OpAMD64VCVTTPS2UQQMasked512,
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ssa.OpAMD64VCVTTPD2UQQMasked128,
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ssa.OpAMD64VCVTTPD2UQQMasked256,
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ssa.OpAMD64VCVTTPD2UQQMasked512,
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ssa.OpAMD64VEXPANDPSMasked128,
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ssa.OpAMD64VEXPANDPSMasked256,
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ssa.OpAMD64VEXPANDPSMasked512,
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@ -1688,12 +1774,55 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
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ssa.OpAMD64VPABSQMasked128load,
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ssa.OpAMD64VPABSQMasked256load,
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ssa.OpAMD64VPABSQMasked512load,
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ssa.OpAMD64VCVTPD2PSXMasked128load,
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ssa.OpAMD64VCVTPD2PSYMasked128load,
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ssa.OpAMD64VCVTPD2PSMasked256load,
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ssa.OpAMD64VCVTDQ2PSMasked128load,
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ssa.OpAMD64VCVTDQ2PSMasked256load,
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ssa.OpAMD64VCVTDQ2PSMasked512load,
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ssa.OpAMD64VCVTQQ2PSXMasked128load,
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ssa.OpAMD64VCVTQQ2PSYMasked128load,
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ssa.OpAMD64VCVTQQ2PSMasked256load,
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ssa.OpAMD64VCVTUDQ2PSMasked128load,
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ssa.OpAMD64VCVTUDQ2PSMasked256load,
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ssa.OpAMD64VCVTUDQ2PSMasked512load,
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ssa.OpAMD64VCVTUQQ2PSXMasked128load,
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ssa.OpAMD64VCVTUQQ2PSYMasked128load,
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ssa.OpAMD64VCVTUQQ2PSMasked256load,
|
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ssa.OpAMD64VCVTPS2PDMasked256load,
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ssa.OpAMD64VCVTPS2PDMasked512load,
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ssa.OpAMD64VCVTDQ2PDMasked256load,
|
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ssa.OpAMD64VCVTDQ2PDMasked512load,
|
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ssa.OpAMD64VCVTQQ2PDMasked128load,
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ssa.OpAMD64VCVTQQ2PDMasked256load,
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ssa.OpAMD64VCVTQQ2PDMasked512load,
|
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ssa.OpAMD64VCVTUDQ2PDMasked256load,
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ssa.OpAMD64VCVTUDQ2PDMasked512load,
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ssa.OpAMD64VCVTUQQ2PDMasked128load,
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ssa.OpAMD64VCVTUQQ2PDMasked256load,
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ssa.OpAMD64VCVTUQQ2PDMasked512load,
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ssa.OpAMD64VCVTTPS2DQMasked128load,
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ssa.OpAMD64VCVTTPS2DQMasked256load,
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ssa.OpAMD64VCVTTPS2DQMasked512load,
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ssa.OpAMD64VCVTPS2UDQMasked128load,
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ssa.OpAMD64VCVTPS2UDQMasked256load,
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ssa.OpAMD64VCVTPS2UDQMasked512load,
|
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ssa.OpAMD64VCVTTPD2DQXMasked128load,
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ssa.OpAMD64VCVTTPD2DQYMasked128load,
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ssa.OpAMD64VCVTTPD2DQMasked256load,
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ssa.OpAMD64VCVTTPS2QQMasked256load,
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ssa.OpAMD64VCVTTPS2QQMasked512load,
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ssa.OpAMD64VCVTTPD2QQMasked128load,
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ssa.OpAMD64VCVTTPD2QQMasked256load,
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ssa.OpAMD64VCVTTPD2QQMasked512load,
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ssa.OpAMD64VCVTTPS2UDQMasked128load,
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ssa.OpAMD64VCVTTPS2UDQMasked256load,
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ssa.OpAMD64VCVTTPS2UDQMasked512load,
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ssa.OpAMD64VCVTTPD2UDQXMasked128load,
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ssa.OpAMD64VCVTTPD2UDQYMasked128load,
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ssa.OpAMD64VCVTTPD2UDQMasked256load,
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ssa.OpAMD64VCVTTPS2UQQMasked256load,
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ssa.OpAMD64VCVTTPS2UQQMasked512load,
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ssa.OpAMD64VCVTTPD2UQQMasked128load,
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ssa.OpAMD64VCVTTPD2UQQMasked256load,
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ssa.OpAMD64VCVTTPD2UQQMasked512load,
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ssa.OpAMD64VPLZCNTDMasked128load,
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ssa.OpAMD64VPLZCNTDMasked256load,
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ssa.OpAMD64VPLZCNTDMasked512load,
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@ -2076,10 +2205,45 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
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ssa.OpAMD64VPABSQ128load,
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ssa.OpAMD64VPABSQ256load,
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ssa.OpAMD64VPABSQ512load,
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ssa.OpAMD64VCVTPD2PS256load,
|
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ssa.OpAMD64VCVTDQ2PS512load,
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ssa.OpAMD64VCVTQQ2PSX128load,
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ssa.OpAMD64VCVTQQ2PSY128load,
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ssa.OpAMD64VCVTQQ2PS256load,
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||||
ssa.OpAMD64VCVTUDQ2PS128load,
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||||
ssa.OpAMD64VCVTUDQ2PS256load,
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||||
ssa.OpAMD64VCVTUDQ2PS512load,
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||||
ssa.OpAMD64VCVTUQQ2PSX128load,
|
||||
ssa.OpAMD64VCVTUQQ2PSY128load,
|
||||
ssa.OpAMD64VCVTUQQ2PS256load,
|
||||
ssa.OpAMD64VCVTPS2PD512load,
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||||
ssa.OpAMD64VCVTDQ2PD512load,
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||||
ssa.OpAMD64VCVTQQ2PD128load,
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ssa.OpAMD64VCVTQQ2PD256load,
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ssa.OpAMD64VCVTQQ2PD512load,
|
||||
ssa.OpAMD64VCVTUDQ2PD256load,
|
||||
ssa.OpAMD64VCVTUDQ2PD512load,
|
||||
ssa.OpAMD64VCVTUQQ2PD128load,
|
||||
ssa.OpAMD64VCVTUQQ2PD256load,
|
||||
ssa.OpAMD64VCVTUQQ2PD512load,
|
||||
ssa.OpAMD64VCVTTPS2DQ512load,
|
||||
ssa.OpAMD64VCVTPS2UDQ128load,
|
||||
ssa.OpAMD64VCVTPS2UDQ256load,
|
||||
ssa.OpAMD64VCVTPS2UDQ512load,
|
||||
ssa.OpAMD64VCVTTPD2DQ256load,
|
||||
ssa.OpAMD64VCVTTPS2QQ256load,
|
||||
ssa.OpAMD64VCVTTPS2QQ512load,
|
||||
ssa.OpAMD64VCVTTPD2QQ128load,
|
||||
ssa.OpAMD64VCVTTPD2QQ256load,
|
||||
ssa.OpAMD64VCVTTPD2QQ512load,
|
||||
ssa.OpAMD64VCVTTPS2UDQ128load,
|
||||
ssa.OpAMD64VCVTTPS2UDQ256load,
|
||||
ssa.OpAMD64VCVTTPS2UDQ512load,
|
||||
ssa.OpAMD64VCVTTPD2UDQX128load,
|
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ssa.OpAMD64VCVTTPD2UDQY128load,
|
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ssa.OpAMD64VCVTTPD2UDQ256load,
|
||||
ssa.OpAMD64VCVTTPS2UQQ256load,
|
||||
ssa.OpAMD64VCVTTPS2UQQ512load,
|
||||
ssa.OpAMD64VCVTTPD2UQQ128load,
|
||||
ssa.OpAMD64VCVTTPD2UQQ256load,
|
||||
ssa.OpAMD64VCVTTPD2UQQ512load,
|
||||
ssa.OpAMD64VPLZCNTD128load,
|
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ssa.OpAMD64VPLZCNTD256load,
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ssa.OpAMD64VPLZCNTD512load,
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@ -2326,12 +2490,55 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
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ssa.OpAMD64VREDUCEPDMasked128Merging,
|
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ssa.OpAMD64VREDUCEPDMasked256Merging,
|
||||
ssa.OpAMD64VREDUCEPDMasked512Merging,
|
||||
ssa.OpAMD64VCVTPD2PSXMasked128Merging,
|
||||
ssa.OpAMD64VCVTPD2PSYMasked128Merging,
|
||||
ssa.OpAMD64VCVTPD2PSMasked256Merging,
|
||||
ssa.OpAMD64VCVTDQ2PSMasked128Merging,
|
||||
ssa.OpAMD64VCVTDQ2PSMasked256Merging,
|
||||
ssa.OpAMD64VCVTDQ2PSMasked512Merging,
|
||||
ssa.OpAMD64VCVTQQ2PSXMasked128Merging,
|
||||
ssa.OpAMD64VCVTQQ2PSYMasked128Merging,
|
||||
ssa.OpAMD64VCVTQQ2PSMasked256Merging,
|
||||
ssa.OpAMD64VCVTUDQ2PSMasked128Merging,
|
||||
ssa.OpAMD64VCVTUDQ2PSMasked256Merging,
|
||||
ssa.OpAMD64VCVTUDQ2PSMasked512Merging,
|
||||
ssa.OpAMD64VCVTUQQ2PSXMasked128Merging,
|
||||
ssa.OpAMD64VCVTUQQ2PSYMasked128Merging,
|
||||
ssa.OpAMD64VCVTUQQ2PSMasked256Merging,
|
||||
ssa.OpAMD64VCVTPS2PDMasked256Merging,
|
||||
ssa.OpAMD64VCVTPS2PDMasked512Merging,
|
||||
ssa.OpAMD64VCVTDQ2PDMasked256Merging,
|
||||
ssa.OpAMD64VCVTDQ2PDMasked512Merging,
|
||||
ssa.OpAMD64VCVTQQ2PDMasked128Merging,
|
||||
ssa.OpAMD64VCVTQQ2PDMasked256Merging,
|
||||
ssa.OpAMD64VCVTQQ2PDMasked512Merging,
|
||||
ssa.OpAMD64VCVTUDQ2PDMasked256Merging,
|
||||
ssa.OpAMD64VCVTUDQ2PDMasked512Merging,
|
||||
ssa.OpAMD64VCVTUQQ2PDMasked128Merging,
|
||||
ssa.OpAMD64VCVTUQQ2PDMasked256Merging,
|
||||
ssa.OpAMD64VCVTUQQ2PDMasked512Merging,
|
||||
ssa.OpAMD64VCVTTPS2DQMasked128Merging,
|
||||
ssa.OpAMD64VCVTTPS2DQMasked256Merging,
|
||||
ssa.OpAMD64VCVTTPS2DQMasked512Merging,
|
||||
ssa.OpAMD64VCVTPS2UDQMasked128Merging,
|
||||
ssa.OpAMD64VCVTPS2UDQMasked256Merging,
|
||||
ssa.OpAMD64VCVTPS2UDQMasked512Merging,
|
||||
ssa.OpAMD64VCVTTPD2DQXMasked128Merging,
|
||||
ssa.OpAMD64VCVTTPD2DQYMasked128Merging,
|
||||
ssa.OpAMD64VCVTTPD2DQMasked256Merging,
|
||||
ssa.OpAMD64VCVTTPS2QQMasked256Merging,
|
||||
ssa.OpAMD64VCVTTPS2QQMasked512Merging,
|
||||
ssa.OpAMD64VCVTTPD2QQMasked128Merging,
|
||||
ssa.OpAMD64VCVTTPD2QQMasked256Merging,
|
||||
ssa.OpAMD64VCVTTPD2QQMasked512Merging,
|
||||
ssa.OpAMD64VCVTTPS2UDQMasked128Merging,
|
||||
ssa.OpAMD64VCVTTPS2UDQMasked256Merging,
|
||||
ssa.OpAMD64VCVTTPS2UDQMasked512Merging,
|
||||
ssa.OpAMD64VCVTTPD2UDQXMasked128Merging,
|
||||
ssa.OpAMD64VCVTTPD2UDQYMasked128Merging,
|
||||
ssa.OpAMD64VCVTTPD2UDQMasked256Merging,
|
||||
ssa.OpAMD64VCVTTPS2UQQMasked256Merging,
|
||||
ssa.OpAMD64VCVTTPS2UQQMasked512Merging,
|
||||
ssa.OpAMD64VCVTTPD2UQQMasked128Merging,
|
||||
ssa.OpAMD64VCVTTPD2UQQMasked256Merging,
|
||||
ssa.OpAMD64VCVTTPD2UQQMasked512Merging,
|
||||
ssa.OpAMD64VPMOVSXBQMasked128Merging,
|
||||
ssa.OpAMD64VPMOVSXWQMasked128Merging,
|
||||
ssa.OpAMD64VPMOVSXDQMasked128Merging,
|
||||
@ -2695,18 +2902,104 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
|
||||
ssa.OpAMD64VPALIGNRMasked256,
|
||||
ssa.OpAMD64VPALIGNRMasked512,
|
||||
ssa.OpAMD64VPALIGNRMasked128,
|
||||
ssa.OpAMD64VCVTPD2PSXMasked128,
|
||||
ssa.OpAMD64VCVTPD2PSXMasked128load,
|
||||
ssa.OpAMD64VCVTPD2PSYMasked128,
|
||||
ssa.OpAMD64VCVTPD2PSYMasked128load,
|
||||
ssa.OpAMD64VCVTPD2PSMasked256,
|
||||
ssa.OpAMD64VCVTPD2PSMasked256load,
|
||||
ssa.OpAMD64VCVTDQ2PSMasked128,
|
||||
ssa.OpAMD64VCVTDQ2PSMasked128load,
|
||||
ssa.OpAMD64VCVTDQ2PSMasked256,
|
||||
ssa.OpAMD64VCVTDQ2PSMasked256load,
|
||||
ssa.OpAMD64VCVTDQ2PSMasked512,
|
||||
ssa.OpAMD64VCVTDQ2PSMasked512load,
|
||||
ssa.OpAMD64VCVTQQ2PSXMasked128,
|
||||
ssa.OpAMD64VCVTQQ2PSXMasked128load,
|
||||
ssa.OpAMD64VCVTQQ2PSYMasked128,
|
||||
ssa.OpAMD64VCVTQQ2PSYMasked128load,
|
||||
ssa.OpAMD64VCVTQQ2PSMasked256,
|
||||
ssa.OpAMD64VCVTQQ2PSMasked256load,
|
||||
ssa.OpAMD64VCVTUDQ2PSMasked128,
|
||||
ssa.OpAMD64VCVTUDQ2PSMasked128load,
|
||||
ssa.OpAMD64VCVTUDQ2PSMasked256,
|
||||
ssa.OpAMD64VCVTUDQ2PSMasked256load,
|
||||
ssa.OpAMD64VCVTUDQ2PSMasked512,
|
||||
ssa.OpAMD64VCVTUDQ2PSMasked512load,
|
||||
ssa.OpAMD64VCVTUQQ2PSXMasked128,
|
||||
ssa.OpAMD64VCVTUQQ2PSXMasked128load,
|
||||
ssa.OpAMD64VCVTUQQ2PSYMasked128,
|
||||
ssa.OpAMD64VCVTUQQ2PSYMasked128load,
|
||||
ssa.OpAMD64VCVTUQQ2PSMasked256,
|
||||
ssa.OpAMD64VCVTUQQ2PSMasked256load,
|
||||
ssa.OpAMD64VCVTPS2PDMasked256,
|
||||
ssa.OpAMD64VCVTPS2PDMasked256load,
|
||||
ssa.OpAMD64VCVTPS2PDMasked512,
|
||||
ssa.OpAMD64VCVTPS2PDMasked512load,
|
||||
ssa.OpAMD64VCVTDQ2PDMasked256,
|
||||
ssa.OpAMD64VCVTDQ2PDMasked256load,
|
||||
ssa.OpAMD64VCVTDQ2PDMasked512,
|
||||
ssa.OpAMD64VCVTDQ2PDMasked512load,
|
||||
ssa.OpAMD64VCVTQQ2PDMasked128,
|
||||
ssa.OpAMD64VCVTQQ2PDMasked128load,
|
||||
ssa.OpAMD64VCVTQQ2PDMasked256,
|
||||
ssa.OpAMD64VCVTQQ2PDMasked256load,
|
||||
ssa.OpAMD64VCVTQQ2PDMasked512,
|
||||
ssa.OpAMD64VCVTQQ2PDMasked512load,
|
||||
ssa.OpAMD64VCVTUDQ2PDMasked256,
|
||||
ssa.OpAMD64VCVTUDQ2PDMasked256load,
|
||||
ssa.OpAMD64VCVTUDQ2PDMasked512,
|
||||
ssa.OpAMD64VCVTUDQ2PDMasked512load,
|
||||
ssa.OpAMD64VCVTUQQ2PDMasked128,
|
||||
ssa.OpAMD64VCVTUQQ2PDMasked128load,
|
||||
ssa.OpAMD64VCVTUQQ2PDMasked256,
|
||||
ssa.OpAMD64VCVTUQQ2PDMasked256load,
|
||||
ssa.OpAMD64VCVTUQQ2PDMasked512,
|
||||
ssa.OpAMD64VCVTUQQ2PDMasked512load,
|
||||
ssa.OpAMD64VCVTTPS2DQMasked128,
|
||||
ssa.OpAMD64VCVTTPS2DQMasked128load,
|
||||
ssa.OpAMD64VCVTTPS2DQMasked256,
|
||||
ssa.OpAMD64VCVTTPS2DQMasked256load,
|
||||
ssa.OpAMD64VCVTTPS2DQMasked512,
|
||||
ssa.OpAMD64VCVTTPS2DQMasked512load,
|
||||
ssa.OpAMD64VCVTPS2UDQMasked128,
|
||||
ssa.OpAMD64VCVTPS2UDQMasked128load,
|
||||
ssa.OpAMD64VCVTPS2UDQMasked256,
|
||||
ssa.OpAMD64VCVTPS2UDQMasked256load,
|
||||
ssa.OpAMD64VCVTPS2UDQMasked512,
|
||||
ssa.OpAMD64VCVTPS2UDQMasked512load,
|
||||
ssa.OpAMD64VCVTTPD2DQXMasked128,
|
||||
ssa.OpAMD64VCVTTPD2DQXMasked128load,
|
||||
ssa.OpAMD64VCVTTPD2DQYMasked128,
|
||||
ssa.OpAMD64VCVTTPD2DQYMasked128load,
|
||||
ssa.OpAMD64VCVTTPD2DQMasked256,
|
||||
ssa.OpAMD64VCVTTPD2DQMasked256load,
|
||||
ssa.OpAMD64VCVTTPS2QQMasked256,
|
||||
ssa.OpAMD64VCVTTPS2QQMasked256load,
|
||||
ssa.OpAMD64VCVTTPS2QQMasked512,
|
||||
ssa.OpAMD64VCVTTPS2QQMasked512load,
|
||||
ssa.OpAMD64VCVTTPD2QQMasked128,
|
||||
ssa.OpAMD64VCVTTPD2QQMasked128load,
|
||||
ssa.OpAMD64VCVTTPD2QQMasked256,
|
||||
ssa.OpAMD64VCVTTPD2QQMasked256load,
|
||||
ssa.OpAMD64VCVTTPD2QQMasked512,
|
||||
ssa.OpAMD64VCVTTPD2QQMasked512load,
|
||||
ssa.OpAMD64VCVTTPS2UDQMasked128,
|
||||
ssa.OpAMD64VCVTTPS2UDQMasked128load,
|
||||
ssa.OpAMD64VCVTTPS2UDQMasked256,
|
||||
ssa.OpAMD64VCVTTPS2UDQMasked256load,
|
||||
ssa.OpAMD64VCVTTPS2UDQMasked512,
|
||||
ssa.OpAMD64VCVTTPS2UDQMasked512load,
|
||||
ssa.OpAMD64VCVTTPD2UDQXMasked128,
|
||||
ssa.OpAMD64VCVTTPD2UDQXMasked128load,
|
||||
ssa.OpAMD64VCVTTPD2UDQYMasked128,
|
||||
ssa.OpAMD64VCVTTPD2UDQYMasked128load,
|
||||
ssa.OpAMD64VCVTTPD2UDQMasked256,
|
||||
ssa.OpAMD64VCVTTPD2UDQMasked256load,
|
||||
ssa.OpAMD64VCVTTPS2UQQMasked256,
|
||||
ssa.OpAMD64VCVTTPS2UQQMasked256load,
|
||||
ssa.OpAMD64VCVTTPS2UQQMasked512,
|
||||
ssa.OpAMD64VCVTTPS2UQQMasked512load,
|
||||
ssa.OpAMD64VCVTTPD2UQQMasked128,
|
||||
ssa.OpAMD64VCVTTPD2UQQMasked128load,
|
||||
ssa.OpAMD64VCVTTPD2UQQMasked256,
|
||||
ssa.OpAMD64VCVTTPD2UQQMasked256load,
|
||||
ssa.OpAMD64VCVTTPD2UQQMasked512,
|
||||
ssa.OpAMD64VCVTTPD2UQQMasked512load,
|
||||
ssa.OpAMD64VDIVPSMasked128,
|
||||
ssa.OpAMD64VDIVPSMasked128load,
|
||||
ssa.OpAMD64VDIVPSMasked256,
|
||||
|
||||
@ -249,12 +249,55 @@
|
||||
(ConcatShiftBytesRightUint8x16 ...) => (VPALIGNR128 ...)
|
||||
(ConcatShiftBytesRightGroupedUint8x32 ...) => (VPALIGNR256 ...)
|
||||
(ConcatShiftBytesRightGroupedUint8x64 ...) => (VPALIGNR512 ...)
|
||||
(ConvertToFloat32Float64x2 ...) => (VCVTPD2PSX128 ...)
|
||||
(ConvertToFloat32Float64x4 ...) => (VCVTPD2PSY128 ...)
|
||||
(ConvertToFloat32Float64x8 ...) => (VCVTPD2PS256 ...)
|
||||
(ConvertToFloat32Int32x4 ...) => (VCVTDQ2PS128 ...)
|
||||
(ConvertToFloat32Int32x8 ...) => (VCVTDQ2PS256 ...)
|
||||
(ConvertToFloat32Int32x16 ...) => (VCVTDQ2PS512 ...)
|
||||
(ConvertToFloat32Int64x2 ...) => (VCVTQQ2PSX128 ...)
|
||||
(ConvertToFloat32Int64x4 ...) => (VCVTQQ2PSY128 ...)
|
||||
(ConvertToFloat32Int64x8 ...) => (VCVTQQ2PS256 ...)
|
||||
(ConvertToFloat32Uint32x4 ...) => (VCVTUDQ2PS128 ...)
|
||||
(ConvertToFloat32Uint32x8 ...) => (VCVTUDQ2PS256 ...)
|
||||
(ConvertToFloat32Uint32x16 ...) => (VCVTUDQ2PS512 ...)
|
||||
(ConvertToFloat32Uint64x2 ...) => (VCVTUQQ2PSX128 ...)
|
||||
(ConvertToFloat32Uint64x4 ...) => (VCVTUQQ2PSY128 ...)
|
||||
(ConvertToFloat32Uint64x8 ...) => (VCVTUQQ2PS256 ...)
|
||||
(ConvertToFloat64Float32x4 ...) => (VCVTPS2PD256 ...)
|
||||
(ConvertToFloat64Float32x8 ...) => (VCVTPS2PD512 ...)
|
||||
(ConvertToFloat64Int32x4 ...) => (VCVTDQ2PD256 ...)
|
||||
(ConvertToFloat64Int32x8 ...) => (VCVTDQ2PD512 ...)
|
||||
(ConvertToFloat64Int64x2 ...) => (VCVTQQ2PD128 ...)
|
||||
(ConvertToFloat64Int64x4 ...) => (VCVTQQ2PD256 ...)
|
||||
(ConvertToFloat64Int64x8 ...) => (VCVTQQ2PD512 ...)
|
||||
(ConvertToFloat64Uint32x4 ...) => (VCVTUDQ2PD256 ...)
|
||||
(ConvertToFloat64Uint32x8 ...) => (VCVTUDQ2PD512 ...)
|
||||
(ConvertToFloat64Uint64x2 ...) => (VCVTUQQ2PD128 ...)
|
||||
(ConvertToFloat64Uint64x4 ...) => (VCVTUQQ2PD256 ...)
|
||||
(ConvertToFloat64Uint64x8 ...) => (VCVTUQQ2PD512 ...)
|
||||
(ConvertToInt32Float32x4 ...) => (VCVTTPS2DQ128 ...)
|
||||
(ConvertToInt32Float32x8 ...) => (VCVTTPS2DQ256 ...)
|
||||
(ConvertToInt32Float32x16 ...) => (VCVTTPS2DQ512 ...)
|
||||
(ConvertToUint32Float32x4 ...) => (VCVTPS2UDQ128 ...)
|
||||
(ConvertToUint32Float32x8 ...) => (VCVTPS2UDQ256 ...)
|
||||
(ConvertToUint32Float32x16 ...) => (VCVTPS2UDQ512 ...)
|
||||
(ConvertToInt32Float64x2 ...) => (VCVTTPD2DQX128 ...)
|
||||
(ConvertToInt32Float64x4 ...) => (VCVTTPD2DQY128 ...)
|
||||
(ConvertToInt32Float64x8 ...) => (VCVTTPD2DQ256 ...)
|
||||
(ConvertToInt64Float32x4 ...) => (VCVTTPS2QQ256 ...)
|
||||
(ConvertToInt64Float32x8 ...) => (VCVTTPS2QQ512 ...)
|
||||
(ConvertToInt64Float64x2 ...) => (VCVTTPD2QQ128 ...)
|
||||
(ConvertToInt64Float64x4 ...) => (VCVTTPD2QQ256 ...)
|
||||
(ConvertToInt64Float64x8 ...) => (VCVTTPD2QQ512 ...)
|
||||
(ConvertToUint32Float32x4 ...) => (VCVTTPS2UDQ128 ...)
|
||||
(ConvertToUint32Float32x8 ...) => (VCVTTPS2UDQ256 ...)
|
||||
(ConvertToUint32Float32x16 ...) => (VCVTTPS2UDQ512 ...)
|
||||
(ConvertToUint32Float64x2 ...) => (VCVTTPD2UDQX128 ...)
|
||||
(ConvertToUint32Float64x4 ...) => (VCVTTPD2UDQY128 ...)
|
||||
(ConvertToUint32Float64x8 ...) => (VCVTTPD2UDQ256 ...)
|
||||
(ConvertToUint64Float32x4 ...) => (VCVTTPS2UQQ256 ...)
|
||||
(ConvertToUint64Float32x8 ...) => (VCVTTPS2UQQ512 ...)
|
||||
(ConvertToUint64Float64x2 ...) => (VCVTTPD2UQQ128 ...)
|
||||
(ConvertToUint64Float64x4 ...) => (VCVTTPD2UQQ256 ...)
|
||||
(ConvertToUint64Float64x8 ...) => (VCVTTPD2UQQ512 ...)
|
||||
(CopySignInt8x16 ...) => (VPSIGNB128 ...)
|
||||
(CopySignInt8x32 ...) => (VPSIGNB256 ...)
|
||||
(CopySignInt16x8 ...) => (VPSIGNW128 ...)
|
||||
@ -1440,12 +1483,55 @@
|
||||
(VMOVDQU8Masked256 (VPALIGNR256 [a] x y) mask) => (VPALIGNRMasked256 [a] x y mask)
|
||||
(VMOVDQU8Masked512 (VPALIGNR512 [a] x y) mask) => (VPALIGNRMasked512 [a] x y mask)
|
||||
(VMOVDQU8Masked128 (VPALIGNR128 [a] x y) mask) => (VPALIGNRMasked128 [a] x y mask)
|
||||
(VMOVDQU64Masked128 (VCVTPD2PSX128 x) mask) => (VCVTPD2PSXMasked128 x mask)
|
||||
(VMOVDQU64Masked128 (VCVTPD2PSY128 x) mask) => (VCVTPD2PSYMasked128 x mask)
|
||||
(VMOVDQU64Masked256 (VCVTPD2PS256 x) mask) => (VCVTPD2PSMasked256 x mask)
|
||||
(VMOVDQU32Masked128 (VCVTDQ2PS128 x) mask) => (VCVTDQ2PSMasked128 x mask)
|
||||
(VMOVDQU32Masked256 (VCVTDQ2PS256 x) mask) => (VCVTDQ2PSMasked256 x mask)
|
||||
(VMOVDQU32Masked512 (VCVTDQ2PS512 x) mask) => (VCVTDQ2PSMasked512 x mask)
|
||||
(VMOVDQU64Masked128 (VCVTQQ2PSX128 x) mask) => (VCVTQQ2PSXMasked128 x mask)
|
||||
(VMOVDQU64Masked128 (VCVTQQ2PSY128 x) mask) => (VCVTQQ2PSYMasked128 x mask)
|
||||
(VMOVDQU64Masked256 (VCVTQQ2PS256 x) mask) => (VCVTQQ2PSMasked256 x mask)
|
||||
(VMOVDQU32Masked128 (VCVTUDQ2PS128 x) mask) => (VCVTUDQ2PSMasked128 x mask)
|
||||
(VMOVDQU32Masked256 (VCVTUDQ2PS256 x) mask) => (VCVTUDQ2PSMasked256 x mask)
|
||||
(VMOVDQU32Masked512 (VCVTUDQ2PS512 x) mask) => (VCVTUDQ2PSMasked512 x mask)
|
||||
(VMOVDQU64Masked128 (VCVTUQQ2PSX128 x) mask) => (VCVTUQQ2PSXMasked128 x mask)
|
||||
(VMOVDQU64Masked128 (VCVTUQQ2PSY128 x) mask) => (VCVTUQQ2PSYMasked128 x mask)
|
||||
(VMOVDQU64Masked256 (VCVTUQQ2PS256 x) mask) => (VCVTUQQ2PSMasked256 x mask)
|
||||
(VMOVDQU32Masked256 (VCVTPS2PD256 x) mask) => (VCVTPS2PDMasked256 x mask)
|
||||
(VMOVDQU32Masked512 (VCVTPS2PD512 x) mask) => (VCVTPS2PDMasked512 x mask)
|
||||
(VMOVDQU32Masked256 (VCVTDQ2PD256 x) mask) => (VCVTDQ2PDMasked256 x mask)
|
||||
(VMOVDQU32Masked512 (VCVTDQ2PD512 x) mask) => (VCVTDQ2PDMasked512 x mask)
|
||||
(VMOVDQU64Masked128 (VCVTQQ2PD128 x) mask) => (VCVTQQ2PDMasked128 x mask)
|
||||
(VMOVDQU64Masked256 (VCVTQQ2PD256 x) mask) => (VCVTQQ2PDMasked256 x mask)
|
||||
(VMOVDQU64Masked512 (VCVTQQ2PD512 x) mask) => (VCVTQQ2PDMasked512 x mask)
|
||||
(VMOVDQU32Masked256 (VCVTUDQ2PD256 x) mask) => (VCVTUDQ2PDMasked256 x mask)
|
||||
(VMOVDQU32Masked512 (VCVTUDQ2PD512 x) mask) => (VCVTUDQ2PDMasked512 x mask)
|
||||
(VMOVDQU64Masked128 (VCVTUQQ2PD128 x) mask) => (VCVTUQQ2PDMasked128 x mask)
|
||||
(VMOVDQU64Masked256 (VCVTUQQ2PD256 x) mask) => (VCVTUQQ2PDMasked256 x mask)
|
||||
(VMOVDQU64Masked512 (VCVTUQQ2PD512 x) mask) => (VCVTUQQ2PDMasked512 x mask)
|
||||
(VMOVDQU32Masked128 (VCVTTPS2DQ128 x) mask) => (VCVTTPS2DQMasked128 x mask)
|
||||
(VMOVDQU32Masked256 (VCVTTPS2DQ256 x) mask) => (VCVTTPS2DQMasked256 x mask)
|
||||
(VMOVDQU32Masked512 (VCVTTPS2DQ512 x) mask) => (VCVTTPS2DQMasked512 x mask)
|
||||
(VMOVDQU32Masked128 (VCVTPS2UDQ128 x) mask) => (VCVTPS2UDQMasked128 x mask)
|
||||
(VMOVDQU32Masked256 (VCVTPS2UDQ256 x) mask) => (VCVTPS2UDQMasked256 x mask)
|
||||
(VMOVDQU32Masked512 (VCVTPS2UDQ512 x) mask) => (VCVTPS2UDQMasked512 x mask)
|
||||
(VMOVDQU64Masked128 (VCVTTPD2DQX128 x) mask) => (VCVTTPD2DQXMasked128 x mask)
|
||||
(VMOVDQU64Masked128 (VCVTTPD2DQY128 x) mask) => (VCVTTPD2DQYMasked128 x mask)
|
||||
(VMOVDQU64Masked256 (VCVTTPD2DQ256 x) mask) => (VCVTTPD2DQMasked256 x mask)
|
||||
(VMOVDQU32Masked256 (VCVTTPS2QQ256 x) mask) => (VCVTTPS2QQMasked256 x mask)
|
||||
(VMOVDQU32Masked512 (VCVTTPS2QQ512 x) mask) => (VCVTTPS2QQMasked512 x mask)
|
||||
(VMOVDQU64Masked128 (VCVTTPD2QQ128 x) mask) => (VCVTTPD2QQMasked128 x mask)
|
||||
(VMOVDQU64Masked256 (VCVTTPD2QQ256 x) mask) => (VCVTTPD2QQMasked256 x mask)
|
||||
(VMOVDQU64Masked512 (VCVTTPD2QQ512 x) mask) => (VCVTTPD2QQMasked512 x mask)
|
||||
(VMOVDQU32Masked128 (VCVTTPS2UDQ128 x) mask) => (VCVTTPS2UDQMasked128 x mask)
|
||||
(VMOVDQU32Masked256 (VCVTTPS2UDQ256 x) mask) => (VCVTTPS2UDQMasked256 x mask)
|
||||
(VMOVDQU32Masked512 (VCVTTPS2UDQ512 x) mask) => (VCVTTPS2UDQMasked512 x mask)
|
||||
(VMOVDQU64Masked128 (VCVTTPD2UDQX128 x) mask) => (VCVTTPD2UDQXMasked128 x mask)
|
||||
(VMOVDQU64Masked128 (VCVTTPD2UDQY128 x) mask) => (VCVTTPD2UDQYMasked128 x mask)
|
||||
(VMOVDQU64Masked256 (VCVTTPD2UDQ256 x) mask) => (VCVTTPD2UDQMasked256 x mask)
|
||||
(VMOVDQU32Masked256 (VCVTTPS2UQQ256 x) mask) => (VCVTTPS2UQQMasked256 x mask)
|
||||
(VMOVDQU32Masked512 (VCVTTPS2UQQ512 x) mask) => (VCVTTPS2UQQMasked512 x mask)
|
||||
(VMOVDQU64Masked128 (VCVTTPD2UQQ128 x) mask) => (VCVTTPD2UQQMasked128 x mask)
|
||||
(VMOVDQU64Masked256 (VCVTTPD2UQQ256 x) mask) => (VCVTTPD2UQQMasked256 x mask)
|
||||
(VMOVDQU64Masked512 (VCVTTPD2UQQ512 x) mask) => (VCVTTPD2UQQMasked512 x mask)
|
||||
(VMOVDQU32Masked128 (VDIVPS128 x y) mask) => (VDIVPSMasked128 x y mask)
|
||||
(VMOVDQU32Masked256 (VDIVPS256 x y) mask) => (VDIVPSMasked256 x y mask)
|
||||
(VMOVDQU32Masked512 (VDIVPS512 x y) mask) => (VDIVPSMasked512 x y mask)
|
||||
@ -1907,8 +1993,10 @@
|
||||
(VPBLENDMBMasked512 dst (VPSUBSB512 x y) mask) => (VPSUBSBMasked512Merging dst x y mask)
|
||||
(VPBLENDMBMasked512 dst (VPSUBUSB512 x y) mask) => (VPSUBUSBMasked512Merging dst x y mask)
|
||||
(VPBLENDMDMasked512 dst (VADDPS512 x y) mask) => (VADDPSMasked512Merging dst x y mask)
|
||||
(VPBLENDMDMasked512 dst (VCVTPS2UDQ512 x) mask) => (VCVTPS2UDQMasked512Merging dst x mask)
|
||||
(VPBLENDMDMasked512 dst (VCVTDQ2PS512 x) mask) => (VCVTDQ2PSMasked512Merging dst x mask)
|
||||
(VPBLENDMDMasked512 dst (VCVTTPS2DQ512 x) mask) => (VCVTTPS2DQMasked512Merging dst x mask)
|
||||
(VPBLENDMDMasked512 dst (VCVTTPS2UDQ512 x) mask) => (VCVTTPS2UDQMasked512Merging dst x mask)
|
||||
(VPBLENDMDMasked512 dst (VCVTUDQ2PS512 x) mask) => (VCVTUDQ2PSMasked512Merging dst x mask)
|
||||
(VPBLENDMDMasked512 dst (VDIVPS512 x y) mask) => (VDIVPSMasked512Merging dst x y mask)
|
||||
(VPBLENDMDMasked512 dst (VMAXPS512 x y) mask) => (VMAXPSMasked512Merging dst x y mask)
|
||||
(VPBLENDMDMasked512 dst (VMINPS512 x y) mask) => (VMINPSMasked512Merging dst x y mask)
|
||||
@ -1953,6 +2041,15 @@
|
||||
(VPBLENDMDMasked512 dst (VSQRTPS512 x) mask) => (VSQRTPSMasked512Merging dst x mask)
|
||||
(VPBLENDMDMasked512 dst (VSUBPS512 x y) mask) => (VSUBPSMasked512Merging dst x y mask)
|
||||
(VPBLENDMQMasked512 dst (VADDPD512 x y) mask) => (VADDPDMasked512Merging dst x y mask)
|
||||
(VPBLENDMQMasked512 dst (VCVTPD2PS256 x) mask) => (VCVTPD2PSMasked256Merging dst x mask)
|
||||
(VPBLENDMQMasked512 dst (VCVTQQ2PD512 x) mask) => (VCVTQQ2PDMasked512Merging dst x mask)
|
||||
(VPBLENDMQMasked512 dst (VCVTQQ2PS256 x) mask) => (VCVTQQ2PSMasked256Merging dst x mask)
|
||||
(VPBLENDMQMasked512 dst (VCVTTPD2DQ256 x) mask) => (VCVTTPD2DQMasked256Merging dst x mask)
|
||||
(VPBLENDMQMasked512 dst (VCVTTPD2QQ512 x) mask) => (VCVTTPD2QQMasked512Merging dst x mask)
|
||||
(VPBLENDMQMasked512 dst (VCVTTPD2UDQ256 x) mask) => (VCVTTPD2UDQMasked256Merging dst x mask)
|
||||
(VPBLENDMQMasked512 dst (VCVTTPD2UQQ512 x) mask) => (VCVTTPD2UQQMasked512Merging dst x mask)
|
||||
(VPBLENDMQMasked512 dst (VCVTUQQ2PD512 x) mask) => (VCVTUQQ2PDMasked512Merging dst x mask)
|
||||
(VPBLENDMQMasked512 dst (VCVTUQQ2PS256 x) mask) => (VCVTUQQ2PSMasked256Merging dst x mask)
|
||||
(VPBLENDMQMasked512 dst (VDIVPD512 x y) mask) => (VDIVPDMasked512Merging dst x y mask)
|
||||
(VPBLENDMQMasked512 dst (VMAXPD512 x y) mask) => (VMAXPDMasked512Merging dst x y mask)
|
||||
(VPBLENDMQMasked512 dst (VMINPD512 x y) mask) => (VMINPDMasked512Merging dst x y mask)
|
||||
@ -2033,8 +2130,24 @@
|
||||
(VPBLENDVB128 dst (VBROADCASTSS128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VBROADCASTSSMasked128Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB128 dst (VBROADCASTSS256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VBROADCASTSSMasked256Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB128 dst (VBROADCASTSS512 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VBROADCASTSSMasked512Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB128 dst (VCVTPS2UDQ128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTPS2UDQMasked128Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB128 dst (VCVTDQ2PD256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTDQ2PDMasked256Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB128 dst (VCVTDQ2PS128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTDQ2PSMasked128Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB128 dst (VCVTPD2PSX128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTPD2PSXMasked128Merging dst x (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB128 dst (VCVTPS2PD256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTPS2PDMasked256Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB128 dst (VCVTQQ2PD128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTQQ2PDMasked128Merging dst x (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB128 dst (VCVTQQ2PSX128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTQQ2PSXMasked128Merging dst x (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB128 dst (VCVTTPD2DQX128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPD2DQXMasked128Merging dst x (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB128 dst (VCVTTPD2QQ128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPD2QQMasked128Merging dst x (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB128 dst (VCVTTPD2UDQX128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPD2UDQXMasked128Merging dst x (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB128 dst (VCVTTPD2UQQ128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPD2UQQMasked128Merging dst x (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB128 dst (VCVTTPS2DQ128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPS2DQMasked128Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB128 dst (VCVTTPS2QQ256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPS2QQMasked256Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB128 dst (VCVTTPS2UDQ128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPS2UDQMasked128Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB128 dst (VCVTTPS2UQQ256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPS2UQQMasked256Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB128 dst (VCVTUDQ2PD256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTUDQ2PDMasked256Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB128 dst (VCVTUDQ2PS128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTUDQ2PSMasked128Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB128 dst (VCVTUQQ2PD128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTUQQ2PDMasked128Merging dst x (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB128 dst (VCVTUQQ2PSX128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTUQQ2PSXMasked128Merging dst x (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB128 dst (VDIVPD128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VDIVPDMasked128Merging dst x y (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB128 dst (VDIVPS128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VDIVPSMasked128Merging dst x y (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB128 dst (VGF2P8MULB128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VGF2P8MULBMasked128Merging dst x y (VPMOVVec8x16ToM <types.TypeMask> mask))
|
||||
@ -2202,8 +2315,24 @@
|
||||
(VPBLENDVB128 dst (VSUBPS128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VSUBPSMasked128Merging dst x y (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB256 dst (VADDPD256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VADDPDMasked256Merging dst x y (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB256 dst (VADDPS256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VADDPSMasked256Merging dst x y (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB256 dst (VCVTPS2UDQ256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTPS2UDQMasked256Merging dst x (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB256 dst (VCVTDQ2PD512 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTDQ2PDMasked512Merging dst x (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB256 dst (VCVTDQ2PS256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTDQ2PSMasked256Merging dst x (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB256 dst (VCVTPD2PSY128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTPD2PSYMasked128Merging dst x (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB256 dst (VCVTPS2PD512 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTPS2PDMasked512Merging dst x (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB256 dst (VCVTQQ2PD256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTQQ2PDMasked256Merging dst x (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB256 dst (VCVTQQ2PSY128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTQQ2PSYMasked128Merging dst x (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB256 dst (VCVTTPD2DQY128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPD2DQYMasked128Merging dst x (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB256 dst (VCVTTPD2QQ256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPD2QQMasked256Merging dst x (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB256 dst (VCVTTPD2UDQY128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPD2UDQYMasked128Merging dst x (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB256 dst (VCVTTPD2UQQ256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPD2UQQMasked256Merging dst x (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB256 dst (VCVTTPS2DQ256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPS2DQMasked256Merging dst x (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB256 dst (VCVTTPS2QQ512 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPS2QQMasked512Merging dst x (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB256 dst (VCVTTPS2UDQ256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPS2UDQMasked256Merging dst x (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB256 dst (VCVTTPS2UQQ512 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPS2UQQMasked512Merging dst x (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB256 dst (VCVTUDQ2PD512 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTUDQ2PDMasked512Merging dst x (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB256 dst (VCVTUDQ2PS256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTUDQ2PSMasked256Merging dst x (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB256 dst (VCVTUQQ2PD256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTUQQ2PDMasked256Merging dst x (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB256 dst (VCVTUQQ2PSY128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTUQQ2PSYMasked128Merging dst x (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB256 dst (VDIVPD256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VDIVPDMasked256Merging dst x y (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB256 dst (VDIVPS256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VDIVPSMasked256Merging dst x y (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB256 dst (VGF2P8MULB256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VGF2P8MULBMasked256Merging dst x y (VPMOVVec8x32ToM <types.TypeMask> mask))
|
||||
@ -2427,16 +2556,94 @@
|
||||
(VPERMI2QMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPERMI2QMasked256load {sym} [off] x y ptr mask mem)
|
||||
(VPERMI2PDMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPERMI2PDMasked512load {sym} [off] x y ptr mask mem)
|
||||
(VPERMI2QMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPERMI2QMasked512load {sym} [off] x y ptr mask mem)
|
||||
(VCVTPD2PS256 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTPD2PS256load {sym} [off] ptr mem)
|
||||
(VCVTDQ2PS512 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTDQ2PS512load {sym} [off] ptr mem)
|
||||
(VCVTQQ2PSX128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTQQ2PSX128load {sym} [off] ptr mem)
|
||||
(VCVTQQ2PSY128 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTQQ2PSY128load {sym} [off] ptr mem)
|
||||
(VCVTQQ2PS256 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTQQ2PS256load {sym} [off] ptr mem)
|
||||
(VCVTUDQ2PS128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTUDQ2PS128load {sym} [off] ptr mem)
|
||||
(VCVTUDQ2PS256 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTUDQ2PS256load {sym} [off] ptr mem)
|
||||
(VCVTUDQ2PS512 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTUDQ2PS512load {sym} [off] ptr mem)
|
||||
(VCVTUQQ2PSX128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTUQQ2PSX128load {sym} [off] ptr mem)
|
||||
(VCVTUQQ2PSY128 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTUQQ2PSY128load {sym} [off] ptr mem)
|
||||
(VCVTUQQ2PS256 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTUQQ2PS256load {sym} [off] ptr mem)
|
||||
(VCVTPD2PSXMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTPD2PSXMasked128load {sym} [off] ptr mask mem)
|
||||
(VCVTPD2PSYMasked128 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTPD2PSYMasked128load {sym} [off] ptr mask mem)
|
||||
(VCVTPD2PSMasked256 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTPD2PSMasked256load {sym} [off] ptr mask mem)
|
||||
(VCVTDQ2PSMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTDQ2PSMasked128load {sym} [off] ptr mask mem)
|
||||
(VCVTDQ2PSMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTDQ2PSMasked256load {sym} [off] ptr mask mem)
|
||||
(VCVTDQ2PSMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTDQ2PSMasked512load {sym} [off] ptr mask mem)
|
||||
(VCVTQQ2PSXMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTQQ2PSXMasked128load {sym} [off] ptr mask mem)
|
||||
(VCVTQQ2PSYMasked128 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTQQ2PSYMasked128load {sym} [off] ptr mask mem)
|
||||
(VCVTQQ2PSMasked256 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTQQ2PSMasked256load {sym} [off] ptr mask mem)
|
||||
(VCVTUDQ2PSMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTUDQ2PSMasked128load {sym} [off] ptr mask mem)
|
||||
(VCVTUDQ2PSMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTUDQ2PSMasked256load {sym} [off] ptr mask mem)
|
||||
(VCVTUDQ2PSMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTUDQ2PSMasked512load {sym} [off] ptr mask mem)
|
||||
(VCVTUQQ2PSXMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTUQQ2PSXMasked128load {sym} [off] ptr mask mem)
|
||||
(VCVTUQQ2PSYMasked128 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTUQQ2PSYMasked128load {sym} [off] ptr mask mem)
|
||||
(VCVTUQQ2PSMasked256 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTUQQ2PSMasked256load {sym} [off] ptr mask mem)
|
||||
(VCVTPS2PD512 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTPS2PD512load {sym} [off] ptr mem)
|
||||
(VCVTDQ2PD512 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTDQ2PD512load {sym} [off] ptr mem)
|
||||
(VCVTQQ2PD128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTQQ2PD128load {sym} [off] ptr mem)
|
||||
(VCVTQQ2PD256 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTQQ2PD256load {sym} [off] ptr mem)
|
||||
(VCVTQQ2PD512 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTQQ2PD512load {sym} [off] ptr mem)
|
||||
(VCVTUDQ2PD256 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTUDQ2PD256load {sym} [off] ptr mem)
|
||||
(VCVTUDQ2PD512 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTUDQ2PD512load {sym} [off] ptr mem)
|
||||
(VCVTUQQ2PD128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTUQQ2PD128load {sym} [off] ptr mem)
|
||||
(VCVTUQQ2PD256 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTUQQ2PD256load {sym} [off] ptr mem)
|
||||
(VCVTUQQ2PD512 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTUQQ2PD512load {sym} [off] ptr mem)
|
||||
(VCVTPS2PDMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTPS2PDMasked256load {sym} [off] ptr mask mem)
|
||||
(VCVTPS2PDMasked512 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTPS2PDMasked512load {sym} [off] ptr mask mem)
|
||||
(VCVTDQ2PDMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTDQ2PDMasked256load {sym} [off] ptr mask mem)
|
||||
(VCVTDQ2PDMasked512 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTDQ2PDMasked512load {sym} [off] ptr mask mem)
|
||||
(VCVTQQ2PDMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTQQ2PDMasked128load {sym} [off] ptr mask mem)
|
||||
(VCVTQQ2PDMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTQQ2PDMasked256load {sym} [off] ptr mask mem)
|
||||
(VCVTQQ2PDMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTQQ2PDMasked512load {sym} [off] ptr mask mem)
|
||||
(VCVTUDQ2PDMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTUDQ2PDMasked256load {sym} [off] ptr mask mem)
|
||||
(VCVTUDQ2PDMasked512 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTUDQ2PDMasked512load {sym} [off] ptr mask mem)
|
||||
(VCVTUQQ2PDMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTUQQ2PDMasked128load {sym} [off] ptr mask mem)
|
||||
(VCVTUQQ2PDMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTUQQ2PDMasked256load {sym} [off] ptr mask mem)
|
||||
(VCVTUQQ2PDMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTUQQ2PDMasked512load {sym} [off] ptr mask mem)
|
||||
(VCVTTPS2DQ512 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2DQ512load {sym} [off] ptr mem)
|
||||
(VCVTTPD2DQ256 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2DQ256load {sym} [off] ptr mem)
|
||||
(VCVTTPS2DQMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2DQMasked128load {sym} [off] ptr mask mem)
|
||||
(VCVTTPS2DQMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2DQMasked256load {sym} [off] ptr mask mem)
|
||||
(VCVTTPS2DQMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2DQMasked512load {sym} [off] ptr mask mem)
|
||||
(VCVTPS2UDQ128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTPS2UDQ128load {sym} [off] ptr mem)
|
||||
(VCVTPS2UDQ256 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTPS2UDQ256load {sym} [off] ptr mem)
|
||||
(VCVTPS2UDQ512 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTPS2UDQ512load {sym} [off] ptr mem)
|
||||
(VCVTPS2UDQMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTPS2UDQMasked128load {sym} [off] ptr mask mem)
|
||||
(VCVTPS2UDQMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTPS2UDQMasked256load {sym} [off] ptr mask mem)
|
||||
(VCVTPS2UDQMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTPS2UDQMasked512load {sym} [off] ptr mask mem)
|
||||
(VCVTTPD2DQXMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2DQXMasked128load {sym} [off] ptr mask mem)
|
||||
(VCVTTPD2DQYMasked128 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2DQYMasked128load {sym} [off] ptr mask mem)
|
||||
(VCVTTPD2DQMasked256 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2DQMasked256load {sym} [off] ptr mask mem)
|
||||
(VCVTTPS2QQ256 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2QQ256load {sym} [off] ptr mem)
|
||||
(VCVTTPS2QQ512 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2QQ512load {sym} [off] ptr mem)
|
||||
(VCVTTPD2QQ128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2QQ128load {sym} [off] ptr mem)
|
||||
(VCVTTPD2QQ256 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2QQ256load {sym} [off] ptr mem)
|
||||
(VCVTTPD2QQ512 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2QQ512load {sym} [off] ptr mem)
|
||||
(VCVTTPS2QQMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2QQMasked256load {sym} [off] ptr mask mem)
|
||||
(VCVTTPS2QQMasked512 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2QQMasked512load {sym} [off] ptr mask mem)
|
||||
(VCVTTPD2QQMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2QQMasked128load {sym} [off] ptr mask mem)
|
||||
(VCVTTPD2QQMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2QQMasked256load {sym} [off] ptr mask mem)
|
||||
(VCVTTPD2QQMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2QQMasked512load {sym} [off] ptr mask mem)
|
||||
(VCVTTPS2UDQ128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2UDQ128load {sym} [off] ptr mem)
|
||||
(VCVTTPS2UDQ256 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2UDQ256load {sym} [off] ptr mem)
|
||||
(VCVTTPS2UDQ512 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2UDQ512load {sym} [off] ptr mem)
|
||||
(VCVTTPD2UDQX128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2UDQX128load {sym} [off] ptr mem)
|
||||
(VCVTTPD2UDQY128 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2UDQY128load {sym} [off] ptr mem)
|
||||
(VCVTTPD2UDQ256 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2UDQ256load {sym} [off] ptr mem)
|
||||
(VCVTTPS2UDQMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2UDQMasked128load {sym} [off] ptr mask mem)
|
||||
(VCVTTPS2UDQMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2UDQMasked256load {sym} [off] ptr mask mem)
|
||||
(VCVTTPS2UDQMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2UDQMasked512load {sym} [off] ptr mask mem)
|
||||
(VCVTTPD2UDQXMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2UDQXMasked128load {sym} [off] ptr mask mem)
|
||||
(VCVTTPD2UDQYMasked128 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2UDQYMasked128load {sym} [off] ptr mask mem)
|
||||
(VCVTTPD2UDQMasked256 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2UDQMasked256load {sym} [off] ptr mask mem)
|
||||
(VCVTTPS2UQQ256 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2UQQ256load {sym} [off] ptr mem)
|
||||
(VCVTTPS2UQQ512 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2UQQ512load {sym} [off] ptr mem)
|
||||
(VCVTTPD2UQQ128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2UQQ128load {sym} [off] ptr mem)
|
||||
(VCVTTPD2UQQ256 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2UQQ256load {sym} [off] ptr mem)
|
||||
(VCVTTPD2UQQ512 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2UQQ512load {sym} [off] ptr mem)
|
||||
(VCVTTPS2UQQMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2UQQMasked256load {sym} [off] ptr mask mem)
|
||||
(VCVTTPS2UQQMasked512 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2UQQMasked512load {sym} [off] ptr mask mem)
|
||||
(VCVTTPD2UQQMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2UQQMasked128load {sym} [off] ptr mask mem)
|
||||
(VCVTTPD2UQQMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2UQQMasked256load {sym} [off] ptr mask mem)
|
||||
(VCVTTPD2UQQMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2UQQMasked512load {sym} [off] ptr mask mem)
|
||||
(VDIVPS512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VDIVPS512load {sym} [off] x ptr mem)
|
||||
(VDIVPD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VDIVPD512load {sym} [off] x ptr mem)
|
||||
(VDIVPSMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VDIVPSMasked128load {sym} [off] x ptr mask mem)
|
||||
|
||||
@ -56,18 +56,104 @@ func simdAMD64Ops(v11, v21, v2k, vkv, v2kv, v2kk, v31, v3kv, vgpv, vgp, vfpv, vf
|
||||
{name: "VCOMPRESSPSMasked128", argLength: 2, reg: wkw, asm: "VCOMPRESSPS", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCOMPRESSPSMasked256", argLength: 2, reg: wkw, asm: "VCOMPRESSPS", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCOMPRESSPSMasked512", argLength: 2, reg: wkw, asm: "VCOMPRESSPS", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VCVTPS2UDQ128", argLength: 1, reg: w11, asm: "VCVTPS2UDQ", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCVTPS2UDQ256", argLength: 1, reg: w11, asm: "VCVTPS2UDQ", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTPS2UDQ512", argLength: 1, reg: w11, asm: "VCVTPS2UDQ", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VCVTPS2UDQMasked128", argLength: 2, reg: wkw, asm: "VCVTPS2UDQ", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCVTPS2UDQMasked256", argLength: 2, reg: wkw, asm: "VCVTPS2UDQ", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTPS2UDQMasked512", argLength: 2, reg: wkw, asm: "VCVTPS2UDQ", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VCVTDQ2PD256", argLength: 1, reg: v11, asm: "VCVTDQ2PD", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTDQ2PD512", argLength: 1, reg: w11, asm: "VCVTDQ2PD", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VCVTDQ2PDMasked256", argLength: 2, reg: wkw, asm: "VCVTDQ2PD", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTDQ2PDMasked512", argLength: 2, reg: wkw, asm: "VCVTDQ2PD", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VCVTDQ2PS128", argLength: 1, reg: v11, asm: "VCVTDQ2PS", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCVTDQ2PS256", argLength: 1, reg: v11, asm: "VCVTDQ2PS", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTDQ2PS512", argLength: 1, reg: w11, asm: "VCVTDQ2PS", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VCVTDQ2PSMasked128", argLength: 2, reg: wkw, asm: "VCVTDQ2PS", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCVTDQ2PSMasked256", argLength: 2, reg: wkw, asm: "VCVTDQ2PS", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTDQ2PSMasked512", argLength: 2, reg: wkw, asm: "VCVTDQ2PS", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VCVTPD2PS256", argLength: 1, reg: w11, asm: "VCVTPD2PS", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTPD2PSMasked256", argLength: 2, reg: wkw, asm: "VCVTPD2PS", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTPD2PSX128", argLength: 1, reg: v11, asm: "VCVTPD2PSX", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCVTPD2PSXMasked128", argLength: 2, reg: wkw, asm: "VCVTPD2PSX", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCVTPD2PSY128", argLength: 1, reg: v11, asm: "VCVTPD2PSY", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCVTPD2PSYMasked128", argLength: 2, reg: wkw, asm: "VCVTPD2PSY", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCVTPS2PD256", argLength: 1, reg: v11, asm: "VCVTPS2PD", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTPS2PD512", argLength: 1, reg: w11, asm: "VCVTPS2PD", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VCVTPS2PDMasked256", argLength: 2, reg: wkw, asm: "VCVTPS2PD", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTPS2PDMasked512", argLength: 2, reg: wkw, asm: "VCVTPS2PD", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VCVTQQ2PD128", argLength: 1, reg: w11, asm: "VCVTQQ2PD", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCVTQQ2PD256", argLength: 1, reg: w11, asm: "VCVTQQ2PD", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTQQ2PD512", argLength: 1, reg: w11, asm: "VCVTQQ2PD", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VCVTQQ2PDMasked128", argLength: 2, reg: wkw, asm: "VCVTQQ2PD", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCVTQQ2PDMasked256", argLength: 2, reg: wkw, asm: "VCVTQQ2PD", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTQQ2PDMasked512", argLength: 2, reg: wkw, asm: "VCVTQQ2PD", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VCVTQQ2PS256", argLength: 1, reg: w11, asm: "VCVTQQ2PS", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTQQ2PSMasked256", argLength: 2, reg: wkw, asm: "VCVTQQ2PS", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTQQ2PSX128", argLength: 1, reg: w11, asm: "VCVTQQ2PSX", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCVTQQ2PSXMasked128", argLength: 2, reg: wkw, asm: "VCVTQQ2PSX", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCVTQQ2PSY128", argLength: 1, reg: w11, asm: "VCVTQQ2PSY", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCVTQQ2PSYMasked128", argLength: 2, reg: wkw, asm: "VCVTQQ2PSY", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCVTTPD2DQ256", argLength: 1, reg: w11, asm: "VCVTTPD2DQ", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTTPD2DQMasked256", argLength: 2, reg: wkw, asm: "VCVTTPD2DQ", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTTPD2DQX128", argLength: 1, reg: v11, asm: "VCVTTPD2DQX", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCVTTPD2DQXMasked128", argLength: 2, reg: wkw, asm: "VCVTTPD2DQX", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCVTTPD2DQY128", argLength: 1, reg: v11, asm: "VCVTTPD2DQY", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCVTTPD2DQYMasked128", argLength: 2, reg: wkw, asm: "VCVTTPD2DQY", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCVTTPD2QQ128", argLength: 1, reg: w11, asm: "VCVTTPD2QQ", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCVTTPD2QQ256", argLength: 1, reg: w11, asm: "VCVTTPD2QQ", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTTPD2QQ512", argLength: 1, reg: w11, asm: "VCVTTPD2QQ", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VCVTTPD2QQMasked128", argLength: 2, reg: wkw, asm: "VCVTTPD2QQ", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCVTTPD2QQMasked256", argLength: 2, reg: wkw, asm: "VCVTTPD2QQ", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTTPD2QQMasked512", argLength: 2, reg: wkw, asm: "VCVTTPD2QQ", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VCVTTPD2UDQ256", argLength: 1, reg: w11, asm: "VCVTTPD2UDQ", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTTPD2UDQMasked256", argLength: 2, reg: wkw, asm: "VCVTTPD2UDQ", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTTPD2UDQX128", argLength: 1, reg: w11, asm: "VCVTTPD2UDQX", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCVTTPD2UDQXMasked128", argLength: 2, reg: wkw, asm: "VCVTTPD2UDQX", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCVTTPD2UDQY128", argLength: 1, reg: w11, asm: "VCVTTPD2UDQY", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCVTTPD2UDQYMasked128", argLength: 2, reg: wkw, asm: "VCVTTPD2UDQY", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCVTTPD2UQQ128", argLength: 1, reg: w11, asm: "VCVTTPD2UQQ", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCVTTPD2UQQ256", argLength: 1, reg: w11, asm: "VCVTTPD2UQQ", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTTPD2UQQ512", argLength: 1, reg: w11, asm: "VCVTTPD2UQQ", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VCVTTPD2UQQMasked128", argLength: 2, reg: wkw, asm: "VCVTTPD2UQQ", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCVTTPD2UQQMasked256", argLength: 2, reg: wkw, asm: "VCVTTPD2UQQ", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTTPD2UQQMasked512", argLength: 2, reg: wkw, asm: "VCVTTPD2UQQ", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VCVTTPS2DQ128", argLength: 1, reg: v11, asm: "VCVTTPS2DQ", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCVTTPS2DQ256", argLength: 1, reg: v11, asm: "VCVTTPS2DQ", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTTPS2DQ512", argLength: 1, reg: w11, asm: "VCVTTPS2DQ", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VCVTTPS2DQMasked128", argLength: 2, reg: wkw, asm: "VCVTTPS2DQ", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCVTTPS2DQMasked256", argLength: 2, reg: wkw, asm: "VCVTTPS2DQ", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTTPS2DQMasked512", argLength: 2, reg: wkw, asm: "VCVTTPS2DQ", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VCVTTPS2QQ256", argLength: 1, reg: w11, asm: "VCVTTPS2QQ", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTTPS2QQ512", argLength: 1, reg: w11, asm: "VCVTTPS2QQ", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VCVTTPS2QQMasked256", argLength: 2, reg: wkw, asm: "VCVTTPS2QQ", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTTPS2QQMasked512", argLength: 2, reg: wkw, asm: "VCVTTPS2QQ", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VCVTTPS2UDQ128", argLength: 1, reg: w11, asm: "VCVTTPS2UDQ", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCVTTPS2UDQ256", argLength: 1, reg: w11, asm: "VCVTTPS2UDQ", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTTPS2UDQ512", argLength: 1, reg: w11, asm: "VCVTTPS2UDQ", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VCVTTPS2UDQMasked128", argLength: 2, reg: wkw, asm: "VCVTTPS2UDQ", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCVTTPS2UDQMasked256", argLength: 2, reg: wkw, asm: "VCVTTPS2UDQ", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTTPS2UDQMasked512", argLength: 2, reg: wkw, asm: "VCVTTPS2UDQ", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VCVTTPS2UQQ256", argLength: 1, reg: w11, asm: "VCVTTPS2UQQ", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTTPS2UQQ512", argLength: 1, reg: w11, asm: "VCVTTPS2UQQ", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VCVTTPS2UQQMasked256", argLength: 2, reg: wkw, asm: "VCVTTPS2UQQ", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTTPS2UQQMasked512", argLength: 2, reg: wkw, asm: "VCVTTPS2UQQ", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VCVTUDQ2PD256", argLength: 1, reg: w11, asm: "VCVTUDQ2PD", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTUDQ2PD512", argLength: 1, reg: w11, asm: "VCVTUDQ2PD", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VCVTUDQ2PDMasked256", argLength: 2, reg: wkw, asm: "VCVTUDQ2PD", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTUDQ2PDMasked512", argLength: 2, reg: wkw, asm: "VCVTUDQ2PD", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VCVTUDQ2PS128", argLength: 1, reg: w11, asm: "VCVTUDQ2PS", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCVTUDQ2PS256", argLength: 1, reg: w11, asm: "VCVTUDQ2PS", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTUDQ2PS512", argLength: 1, reg: w11, asm: "VCVTUDQ2PS", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VCVTUDQ2PSMasked128", argLength: 2, reg: wkw, asm: "VCVTUDQ2PS", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCVTUDQ2PSMasked256", argLength: 2, reg: wkw, asm: "VCVTUDQ2PS", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTUDQ2PSMasked512", argLength: 2, reg: wkw, asm: "VCVTUDQ2PS", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VCVTUQQ2PD128", argLength: 1, reg: w11, asm: "VCVTUQQ2PD", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCVTUQQ2PD256", argLength: 1, reg: w11, asm: "VCVTUQQ2PD", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTUQQ2PD512", argLength: 1, reg: w11, asm: "VCVTUQQ2PD", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VCVTUQQ2PDMasked128", argLength: 2, reg: wkw, asm: "VCVTUQQ2PD", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCVTUQQ2PDMasked256", argLength: 2, reg: wkw, asm: "VCVTUQQ2PD", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTUQQ2PDMasked512", argLength: 2, reg: wkw, asm: "VCVTUQQ2PD", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VCVTUQQ2PS256", argLength: 1, reg: w11, asm: "VCVTUQQ2PS", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTUQQ2PSMasked256", argLength: 2, reg: wkw, asm: "VCVTUQQ2PS", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTUQQ2PSX128", argLength: 1, reg: w11, asm: "VCVTUQQ2PSX", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCVTUQQ2PSXMasked128", argLength: 2, reg: wkw, asm: "VCVTUQQ2PSX", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCVTUQQ2PSY128", argLength: 1, reg: w11, asm: "VCVTUQQ2PSY", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCVTUQQ2PSYMasked128", argLength: 2, reg: wkw, asm: "VCVTUQQ2PSY", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VDIVPD128", argLength: 2, reg: v21, asm: "VDIVPD", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VDIVPD256", argLength: 2, reg: v21, asm: "VDIVPD", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VDIVPD512", argLength: 2, reg: w21, asm: "VDIVPD", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
@ -1145,18 +1231,18 @@ func simdAMD64Ops(v11, v21, v2k, vkv, v2kv, v2kk, v31, v3kv, vgpv, vgp, vfpv, vf
|
||||
{name: "VSUBPSMasked512", argLength: 3, reg: w2kw, asm: "VSUBPS", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "SHA1RNDS4128", argLength: 2, reg: v21, asm: "SHA1RNDS4", aux: "UInt8", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VAESKEYGENASSIST128", argLength: 1, reg: v11, asm: "VAESKEYGENASSIST", aux: "UInt8", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCMPPD128", argLength: 2, reg: v21, asm: "VCMPPD", aux: "UInt8", commutative: true, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCMPPD256", argLength: 2, reg: v21, asm: "VCMPPD", aux: "UInt8", commutative: true, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCMPPD512", argLength: 2, reg: w2k, asm: "VCMPPD", aux: "UInt8", commutative: true, typ: "Mask", resultInArg0: false},
|
||||
{name: "VCMPPDMasked128", argLength: 3, reg: w2kk, asm: "VCMPPD", aux: "UInt8", commutative: true, typ: "Mask", resultInArg0: false},
|
||||
{name: "VCMPPDMasked256", argLength: 3, reg: w2kk, asm: "VCMPPD", aux: "UInt8", commutative: true, typ: "Mask", resultInArg0: false},
|
||||
{name: "VCMPPDMasked512", argLength: 3, reg: w2kk, asm: "VCMPPD", aux: "UInt8", commutative: true, typ: "Mask", resultInArg0: false},
|
||||
{name: "VCMPPS128", argLength: 2, reg: v21, asm: "VCMPPS", aux: "UInt8", commutative: true, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCMPPS256", argLength: 2, reg: v21, asm: "VCMPPS", aux: "UInt8", commutative: true, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCMPPS512", argLength: 2, reg: w2k, asm: "VCMPPS", aux: "UInt8", commutative: true, typ: "Mask", resultInArg0: false},
|
||||
{name: "VCMPPSMasked128", argLength: 3, reg: w2kk, asm: "VCMPPS", aux: "UInt8", commutative: true, typ: "Mask", resultInArg0: false},
|
||||
{name: "VCMPPSMasked256", argLength: 3, reg: w2kk, asm: "VCMPPS", aux: "UInt8", commutative: true, typ: "Mask", resultInArg0: false},
|
||||
{name: "VCMPPSMasked512", argLength: 3, reg: w2kk, asm: "VCMPPS", aux: "UInt8", commutative: true, typ: "Mask", resultInArg0: false},
|
||||
{name: "VCMPPD128", argLength: 2, reg: v21, asm: "VCMPPD", aux: "UInt8", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCMPPD256", argLength: 2, reg: v21, asm: "VCMPPD", aux: "UInt8", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCMPPD512", argLength: 2, reg: w2k, asm: "VCMPPD", aux: "UInt8", commutative: false, typ: "Mask", resultInArg0: false},
|
||||
{name: "VCMPPDMasked128", argLength: 3, reg: w2kk, asm: "VCMPPD", aux: "UInt8", commutative: false, typ: "Mask", resultInArg0: false},
|
||||
{name: "VCMPPDMasked256", argLength: 3, reg: w2kk, asm: "VCMPPD", aux: "UInt8", commutative: false, typ: "Mask", resultInArg0: false},
|
||||
{name: "VCMPPDMasked512", argLength: 3, reg: w2kk, asm: "VCMPPD", aux: "UInt8", commutative: false, typ: "Mask", resultInArg0: false},
|
||||
{name: "VCMPPS128", argLength: 2, reg: v21, asm: "VCMPPS", aux: "UInt8", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCMPPS256", argLength: 2, reg: v21, asm: "VCMPPS", aux: "UInt8", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCMPPS512", argLength: 2, reg: w2k, asm: "VCMPPS", aux: "UInt8", commutative: false, typ: "Mask", resultInArg0: false},
|
||||
{name: "VCMPPSMasked128", argLength: 3, reg: w2kk, asm: "VCMPPS", aux: "UInt8", commutative: false, typ: "Mask", resultInArg0: false},
|
||||
{name: "VCMPPSMasked256", argLength: 3, reg: w2kk, asm: "VCMPPS", aux: "UInt8", commutative: false, typ: "Mask", resultInArg0: false},
|
||||
{name: "VCMPPSMasked512", argLength: 3, reg: w2kk, asm: "VCMPPS", aux: "UInt8", commutative: false, typ: "Mask", resultInArg0: false},
|
||||
{name: "VEXTRACTF64X4256", argLength: 1, reg: w11, asm: "VEXTRACTF64X4", aux: "UInt8", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VEXTRACTF128128", argLength: 1, reg: v11, asm: "VEXTRACTF128", aux: "UInt8", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VEXTRACTI64X4256", argLength: 1, reg: w11, asm: "VEXTRACTI64X4", aux: "UInt8", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
@ -1184,37 +1270,37 @@ func simdAMD64Ops(v11, v21, v2k, vkv, v2kv, v2kk, v31, v3kv, vgpv, vgp, vfpv, vf
|
||||
{name: "VPALIGNRMasked256", argLength: 3, reg: w2kw, asm: "VPALIGNR", aux: "UInt8", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VPALIGNRMasked512", argLength: 3, reg: w2kw, asm: "VPALIGNR", aux: "UInt8", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VPCMPB512", argLength: 2, reg: w2k, asm: "VPCMPB", aux: "UInt8", commutative: false, typ: "Mask", resultInArg0: false},
|
||||
{name: "VPCMPBMasked128", argLength: 3, reg: w2kk, asm: "VPCMPB", aux: "UInt8", commutative: true, typ: "Mask", resultInArg0: false},
|
||||
{name: "VPCMPBMasked256", argLength: 3, reg: w2kk, asm: "VPCMPB", aux: "UInt8", commutative: true, typ: "Mask", resultInArg0: false},
|
||||
{name: "VPCMPBMasked512", argLength: 3, reg: w2kk, asm: "VPCMPB", aux: "UInt8", commutative: true, typ: "Mask", resultInArg0: false},
|
||||
{name: "VPCMPBMasked128", argLength: 3, reg: w2kk, asm: "VPCMPB", aux: "UInt8", commutative: false, typ: "Mask", resultInArg0: false},
|
||||
{name: "VPCMPBMasked256", argLength: 3, reg: w2kk, asm: "VPCMPB", aux: "UInt8", commutative: false, typ: "Mask", resultInArg0: false},
|
||||
{name: "VPCMPBMasked512", argLength: 3, reg: w2kk, asm: "VPCMPB", aux: "UInt8", commutative: false, typ: "Mask", resultInArg0: false},
|
||||
{name: "VPCMPD512", argLength: 2, reg: w2k, asm: "VPCMPD", aux: "UInt8", commutative: false, typ: "Mask", resultInArg0: false},
|
||||
{name: "VPCMPDMasked128", argLength: 3, reg: w2kk, asm: "VPCMPD", aux: "UInt8", commutative: true, typ: "Mask", resultInArg0: false},
|
||||
{name: "VPCMPDMasked256", argLength: 3, reg: w2kk, asm: "VPCMPD", aux: "UInt8", commutative: true, typ: "Mask", resultInArg0: false},
|
||||
{name: "VPCMPDMasked512", argLength: 3, reg: w2kk, asm: "VPCMPD", aux: "UInt8", commutative: true, typ: "Mask", resultInArg0: false},
|
||||
{name: "VPCMPDMasked128", argLength: 3, reg: w2kk, asm: "VPCMPD", aux: "UInt8", commutative: false, typ: "Mask", resultInArg0: false},
|
||||
{name: "VPCMPDMasked256", argLength: 3, reg: w2kk, asm: "VPCMPD", aux: "UInt8", commutative: false, typ: "Mask", resultInArg0: false},
|
||||
{name: "VPCMPDMasked512", argLength: 3, reg: w2kk, asm: "VPCMPD", aux: "UInt8", commutative: false, typ: "Mask", resultInArg0: false},
|
||||
{name: "VPCMPQ512", argLength: 2, reg: w2k, asm: "VPCMPQ", aux: "UInt8", commutative: false, typ: "Mask", resultInArg0: false},
|
||||
{name: "VPCMPQMasked128", argLength: 3, reg: w2kk, asm: "VPCMPQ", aux: "UInt8", commutative: true, typ: "Mask", resultInArg0: false},
|
||||
{name: "VPCMPQMasked256", argLength: 3, reg: w2kk, asm: "VPCMPQ", aux: "UInt8", commutative: true, typ: "Mask", resultInArg0: false},
|
||||
{name: "VPCMPQMasked512", argLength: 3, reg: w2kk, asm: "VPCMPQ", aux: "UInt8", commutative: true, typ: "Mask", resultInArg0: false},
|
||||
{name: "VPCMPQMasked128", argLength: 3, reg: w2kk, asm: "VPCMPQ", aux: "UInt8", commutative: false, typ: "Mask", resultInArg0: false},
|
||||
{name: "VPCMPQMasked256", argLength: 3, reg: w2kk, asm: "VPCMPQ", aux: "UInt8", commutative: false, typ: "Mask", resultInArg0: false},
|
||||
{name: "VPCMPQMasked512", argLength: 3, reg: w2kk, asm: "VPCMPQ", aux: "UInt8", commutative: false, typ: "Mask", resultInArg0: false},
|
||||
{name: "VPCMPUB512", argLength: 2, reg: w2k, asm: "VPCMPUB", aux: "UInt8", commutative: false, typ: "Mask", resultInArg0: false},
|
||||
{name: "VPCMPUBMasked128", argLength: 3, reg: w2kk, asm: "VPCMPUB", aux: "UInt8", commutative: true, typ: "Mask", resultInArg0: false},
|
||||
{name: "VPCMPUBMasked256", argLength: 3, reg: w2kk, asm: "VPCMPUB", aux: "UInt8", commutative: true, typ: "Mask", resultInArg0: false},
|
||||
{name: "VPCMPUBMasked512", argLength: 3, reg: w2kk, asm: "VPCMPUB", aux: "UInt8", commutative: true, typ: "Mask", resultInArg0: false},
|
||||
{name: "VPCMPUBMasked128", argLength: 3, reg: w2kk, asm: "VPCMPUB", aux: "UInt8", commutative: false, typ: "Mask", resultInArg0: false},
|
||||
{name: "VPCMPUBMasked256", argLength: 3, reg: w2kk, asm: "VPCMPUB", aux: "UInt8", commutative: false, typ: "Mask", resultInArg0: false},
|
||||
{name: "VPCMPUBMasked512", argLength: 3, reg: w2kk, asm: "VPCMPUB", aux: "UInt8", commutative: false, typ: "Mask", resultInArg0: false},
|
||||
{name: "VPCMPUD512", argLength: 2, reg: w2k, asm: "VPCMPUD", aux: "UInt8", commutative: false, typ: "Mask", resultInArg0: false},
|
||||
{name: "VPCMPUDMasked128", argLength: 3, reg: w2kk, asm: "VPCMPUD", aux: "UInt8", commutative: true, typ: "Mask", resultInArg0: false},
|
||||
{name: "VPCMPUDMasked256", argLength: 3, reg: w2kk, asm: "VPCMPUD", aux: "UInt8", commutative: true, typ: "Mask", resultInArg0: false},
|
||||
{name: "VPCMPUDMasked512", argLength: 3, reg: w2kk, asm: "VPCMPUD", aux: "UInt8", commutative: true, typ: "Mask", resultInArg0: false},
|
||||
{name: "VPCMPUDMasked128", argLength: 3, reg: w2kk, asm: "VPCMPUD", aux: "UInt8", commutative: false, typ: "Mask", resultInArg0: false},
|
||||
{name: "VPCMPUDMasked256", argLength: 3, reg: w2kk, asm: "VPCMPUD", aux: "UInt8", commutative: false, typ: "Mask", resultInArg0: false},
|
||||
{name: "VPCMPUDMasked512", argLength: 3, reg: w2kk, asm: "VPCMPUD", aux: "UInt8", commutative: false, typ: "Mask", resultInArg0: false},
|
||||
{name: "VPCMPUQ512", argLength: 2, reg: w2k, asm: "VPCMPUQ", aux: "UInt8", commutative: false, typ: "Mask", resultInArg0: false},
|
||||
{name: "VPCMPUQMasked128", argLength: 3, reg: w2kk, asm: "VPCMPUQ", aux: "UInt8", commutative: true, typ: "Mask", resultInArg0: false},
|
||||
{name: "VPCMPUQMasked256", argLength: 3, reg: w2kk, asm: "VPCMPUQ", aux: "UInt8", commutative: true, typ: "Mask", resultInArg0: false},
|
||||
{name: "VPCMPUQMasked512", argLength: 3, reg: w2kk, asm: "VPCMPUQ", aux: "UInt8", commutative: true, typ: "Mask", resultInArg0: false},
|
||||
{name: "VPCMPUQMasked128", argLength: 3, reg: w2kk, asm: "VPCMPUQ", aux: "UInt8", commutative: false, typ: "Mask", resultInArg0: false},
|
||||
{name: "VPCMPUQMasked256", argLength: 3, reg: w2kk, asm: "VPCMPUQ", aux: "UInt8", commutative: false, typ: "Mask", resultInArg0: false},
|
||||
{name: "VPCMPUQMasked512", argLength: 3, reg: w2kk, asm: "VPCMPUQ", aux: "UInt8", commutative: false, typ: "Mask", resultInArg0: false},
|
||||
{name: "VPCMPUW512", argLength: 2, reg: w2k, asm: "VPCMPUW", aux: "UInt8", commutative: false, typ: "Mask", resultInArg0: false},
|
||||
{name: "VPCMPUWMasked128", argLength: 3, reg: w2kk, asm: "VPCMPUW", aux: "UInt8", commutative: true, typ: "Mask", resultInArg0: false},
|
||||
{name: "VPCMPUWMasked256", argLength: 3, reg: w2kk, asm: "VPCMPUW", aux: "UInt8", commutative: true, typ: "Mask", resultInArg0: false},
|
||||
{name: "VPCMPUWMasked512", argLength: 3, reg: w2kk, asm: "VPCMPUW", aux: "UInt8", commutative: true, typ: "Mask", resultInArg0: false},
|
||||
{name: "VPCMPUWMasked128", argLength: 3, reg: w2kk, asm: "VPCMPUW", aux: "UInt8", commutative: false, typ: "Mask", resultInArg0: false},
|
||||
{name: "VPCMPUWMasked256", argLength: 3, reg: w2kk, asm: "VPCMPUW", aux: "UInt8", commutative: false, typ: "Mask", resultInArg0: false},
|
||||
{name: "VPCMPUWMasked512", argLength: 3, reg: w2kk, asm: "VPCMPUW", aux: "UInt8", commutative: false, typ: "Mask", resultInArg0: false},
|
||||
{name: "VPCMPW512", argLength: 2, reg: w2k, asm: "VPCMPW", aux: "UInt8", commutative: false, typ: "Mask", resultInArg0: false},
|
||||
{name: "VPCMPWMasked128", argLength: 3, reg: w2kk, asm: "VPCMPW", aux: "UInt8", commutative: true, typ: "Mask", resultInArg0: false},
|
||||
{name: "VPCMPWMasked256", argLength: 3, reg: w2kk, asm: "VPCMPW", aux: "UInt8", commutative: true, typ: "Mask", resultInArg0: false},
|
||||
{name: "VPCMPWMasked512", argLength: 3, reg: w2kk, asm: "VPCMPW", aux: "UInt8", commutative: true, typ: "Mask", resultInArg0: false},
|
||||
{name: "VPCMPWMasked128", argLength: 3, reg: w2kk, asm: "VPCMPW", aux: "UInt8", commutative: false, typ: "Mask", resultInArg0: false},
|
||||
{name: "VPCMPWMasked256", argLength: 3, reg: w2kk, asm: "VPCMPW", aux: "UInt8", commutative: false, typ: "Mask", resultInArg0: false},
|
||||
{name: "VPCMPWMasked512", argLength: 3, reg: w2kk, asm: "VPCMPW", aux: "UInt8", commutative: false, typ: "Mask", resultInArg0: false},
|
||||
{name: "VPERM2F128256", argLength: 2, reg: v21, asm: "VPERM2F128", aux: "UInt8", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VPERM2I128256", argLength: 2, reg: v21, asm: "VPERM2I128", aux: "UInt8", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VPEXTRB128", argLength: 1, reg: wgp, asm: "VPEXTRB", aux: "UInt8", commutative: false, typ: "int8", resultInArg0: false},
|
||||
@ -1405,16 +1491,94 @@ func simdAMD64Ops(v11, v21, v2k, vkv, v2kv, v2kk, v31, v3kv, vgpv, vgp, vfpv, vf
|
||||
{name: "VADDPSMasked128load", argLength: 4, reg: w2kwload, asm: "VADDPS", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VADDPSMasked256load", argLength: 4, reg: w2kwload, asm: "VADDPS", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VADDPSMasked512load", argLength: 4, reg: w2kwload, asm: "VADDPS", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTPS2UDQ128load", argLength: 2, reg: w11load, asm: "VCVTPS2UDQ", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTPS2UDQ256load", argLength: 2, reg: w11load, asm: "VCVTPS2UDQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTPS2UDQ512load", argLength: 2, reg: w11load, asm: "VCVTPS2UDQ", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTPS2UDQMasked128load", argLength: 3, reg: wkwload, asm: "VCVTPS2UDQ", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTPS2UDQMasked256load", argLength: 3, reg: wkwload, asm: "VCVTPS2UDQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTPS2UDQMasked512load", argLength: 3, reg: wkwload, asm: "VCVTPS2UDQ", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTDQ2PD512load", argLength: 2, reg: w11load, asm: "VCVTDQ2PD", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTDQ2PDMasked256load", argLength: 3, reg: wkwload, asm: "VCVTDQ2PD", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTDQ2PDMasked512load", argLength: 3, reg: wkwload, asm: "VCVTDQ2PD", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTDQ2PS512load", argLength: 2, reg: w11load, asm: "VCVTDQ2PS", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTDQ2PSMasked128load", argLength: 3, reg: wkwload, asm: "VCVTDQ2PS", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTDQ2PSMasked256load", argLength: 3, reg: wkwload, asm: "VCVTDQ2PS", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTDQ2PSMasked512load", argLength: 3, reg: wkwload, asm: "VCVTDQ2PS", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTPD2PS256load", argLength: 2, reg: w11load, asm: "VCVTPD2PS", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTPD2PSMasked256load", argLength: 3, reg: wkwload, asm: "VCVTPD2PS", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTPD2PSXMasked128load", argLength: 3, reg: wkwload, asm: "VCVTPD2PSX", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTPD2PSYMasked128load", argLength: 3, reg: wkwload, asm: "VCVTPD2PSY", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTPS2PD512load", argLength: 2, reg: w11load, asm: "VCVTPS2PD", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTPS2PDMasked256load", argLength: 3, reg: wkwload, asm: "VCVTPS2PD", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTPS2PDMasked512load", argLength: 3, reg: wkwload, asm: "VCVTPS2PD", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTQQ2PD128load", argLength: 2, reg: w11load, asm: "VCVTQQ2PD", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTQQ2PD256load", argLength: 2, reg: w11load, asm: "VCVTQQ2PD", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTQQ2PD512load", argLength: 2, reg: w11load, asm: "VCVTQQ2PD", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTQQ2PDMasked128load", argLength: 3, reg: wkwload, asm: "VCVTQQ2PD", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTQQ2PDMasked256load", argLength: 3, reg: wkwload, asm: "VCVTQQ2PD", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTQQ2PDMasked512load", argLength: 3, reg: wkwload, asm: "VCVTQQ2PD", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTQQ2PS256load", argLength: 2, reg: w11load, asm: "VCVTQQ2PS", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTQQ2PSMasked256load", argLength: 3, reg: wkwload, asm: "VCVTQQ2PS", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTQQ2PSX128load", argLength: 2, reg: w11load, asm: "VCVTQQ2PSX", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTQQ2PSXMasked128load", argLength: 3, reg: wkwload, asm: "VCVTQQ2PSX", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTQQ2PSY128load", argLength: 2, reg: w11load, asm: "VCVTQQ2PSY", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTQQ2PSYMasked128load", argLength: 3, reg: wkwload, asm: "VCVTQQ2PSY", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPD2DQ256load", argLength: 2, reg: w11load, asm: "VCVTTPD2DQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPD2DQMasked256load", argLength: 3, reg: wkwload, asm: "VCVTTPD2DQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPD2DQXMasked128load", argLength: 3, reg: wkwload, asm: "VCVTTPD2DQX", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPD2DQYMasked128load", argLength: 3, reg: wkwload, asm: "VCVTTPD2DQY", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPD2QQ128load", argLength: 2, reg: w11load, asm: "VCVTTPD2QQ", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPD2QQ256load", argLength: 2, reg: w11load, asm: "VCVTTPD2QQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPD2QQ512load", argLength: 2, reg: w11load, asm: "VCVTTPD2QQ", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPD2QQMasked128load", argLength: 3, reg: wkwload, asm: "VCVTTPD2QQ", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPD2QQMasked256load", argLength: 3, reg: wkwload, asm: "VCVTTPD2QQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPD2QQMasked512load", argLength: 3, reg: wkwload, asm: "VCVTTPD2QQ", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPD2UDQ256load", argLength: 2, reg: w11load, asm: "VCVTTPD2UDQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPD2UDQMasked256load", argLength: 3, reg: wkwload, asm: "VCVTTPD2UDQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPD2UDQX128load", argLength: 2, reg: w11load, asm: "VCVTTPD2UDQX", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPD2UDQXMasked128load", argLength: 3, reg: wkwload, asm: "VCVTTPD2UDQX", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPD2UDQY128load", argLength: 2, reg: w11load, asm: "VCVTTPD2UDQY", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPD2UDQYMasked128load", argLength: 3, reg: wkwload, asm: "VCVTTPD2UDQY", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPD2UQQ128load", argLength: 2, reg: w11load, asm: "VCVTTPD2UQQ", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPD2UQQ256load", argLength: 2, reg: w11load, asm: "VCVTTPD2UQQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPD2UQQ512load", argLength: 2, reg: w11load, asm: "VCVTTPD2UQQ", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPD2UQQMasked128load", argLength: 3, reg: wkwload, asm: "VCVTTPD2UQQ", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPD2UQQMasked256load", argLength: 3, reg: wkwload, asm: "VCVTTPD2UQQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPD2UQQMasked512load", argLength: 3, reg: wkwload, asm: "VCVTTPD2UQQ", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPS2DQ512load", argLength: 2, reg: w11load, asm: "VCVTTPS2DQ", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPS2DQMasked128load", argLength: 3, reg: wkwload, asm: "VCVTTPS2DQ", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPS2DQMasked256load", argLength: 3, reg: wkwload, asm: "VCVTTPS2DQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPS2DQMasked512load", argLength: 3, reg: wkwload, asm: "VCVTTPS2DQ", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPS2QQ256load", argLength: 2, reg: w11load, asm: "VCVTTPS2QQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPS2QQ512load", argLength: 2, reg: w11load, asm: "VCVTTPS2QQ", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPS2QQMasked256load", argLength: 3, reg: wkwload, asm: "VCVTTPS2QQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPS2QQMasked512load", argLength: 3, reg: wkwload, asm: "VCVTTPS2QQ", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPS2UDQ128load", argLength: 2, reg: w11load, asm: "VCVTTPS2UDQ", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPS2UDQ256load", argLength: 2, reg: w11load, asm: "VCVTTPS2UDQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPS2UDQ512load", argLength: 2, reg: w11load, asm: "VCVTTPS2UDQ", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPS2UDQMasked128load", argLength: 3, reg: wkwload, asm: "VCVTTPS2UDQ", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPS2UDQMasked256load", argLength: 3, reg: wkwload, asm: "VCVTTPS2UDQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPS2UDQMasked512load", argLength: 3, reg: wkwload, asm: "VCVTTPS2UDQ", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPS2UQQ256load", argLength: 2, reg: w11load, asm: "VCVTTPS2UQQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPS2UQQ512load", argLength: 2, reg: w11load, asm: "VCVTTPS2UQQ", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPS2UQQMasked256load", argLength: 3, reg: wkwload, asm: "VCVTTPS2UQQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPS2UQQMasked512load", argLength: 3, reg: wkwload, asm: "VCVTTPS2UQQ", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTUDQ2PD256load", argLength: 2, reg: w11load, asm: "VCVTUDQ2PD", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTUDQ2PD512load", argLength: 2, reg: w11load, asm: "VCVTUDQ2PD", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTUDQ2PDMasked256load", argLength: 3, reg: wkwload, asm: "VCVTUDQ2PD", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTUDQ2PDMasked512load", argLength: 3, reg: wkwload, asm: "VCVTUDQ2PD", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTUDQ2PS128load", argLength: 2, reg: w11load, asm: "VCVTUDQ2PS", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTUDQ2PS256load", argLength: 2, reg: w11load, asm: "VCVTUDQ2PS", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTUDQ2PS512load", argLength: 2, reg: w11load, asm: "VCVTUDQ2PS", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTUDQ2PSMasked128load", argLength: 3, reg: wkwload, asm: "VCVTUDQ2PS", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTUDQ2PSMasked256load", argLength: 3, reg: wkwload, asm: "VCVTUDQ2PS", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTUDQ2PSMasked512load", argLength: 3, reg: wkwload, asm: "VCVTUDQ2PS", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTUQQ2PD128load", argLength: 2, reg: w11load, asm: "VCVTUQQ2PD", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTUQQ2PD256load", argLength: 2, reg: w11load, asm: "VCVTUQQ2PD", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTUQQ2PD512load", argLength: 2, reg: w11load, asm: "VCVTUQQ2PD", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTUQQ2PDMasked128load", argLength: 3, reg: wkwload, asm: "VCVTUQQ2PD", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTUQQ2PDMasked256load", argLength: 3, reg: wkwload, asm: "VCVTUQQ2PD", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTUQQ2PDMasked512load", argLength: 3, reg: wkwload, asm: "VCVTUQQ2PD", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTUQQ2PS256load", argLength: 2, reg: w11load, asm: "VCVTUQQ2PS", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTUQQ2PSMasked256load", argLength: 3, reg: wkwload, asm: "VCVTUQQ2PS", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTUQQ2PSX128load", argLength: 2, reg: w11load, asm: "VCVTUQQ2PSX", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTUQQ2PSXMasked128load", argLength: 3, reg: wkwload, asm: "VCVTUQQ2PSX", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTUQQ2PSY128load", argLength: 2, reg: w11load, asm: "VCVTUQQ2PSY", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTUQQ2PSYMasked128load", argLength: 3, reg: wkwload, asm: "VCVTUQQ2PSY", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VDIVPD512load", argLength: 3, reg: w21load, asm: "VDIVPD", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VDIVPDMasked128load", argLength: 4, reg: w2kwload, asm: "VDIVPD", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VDIVPDMasked256load", argLength: 4, reg: w2kwload, asm: "VDIVPD", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
@ -1962,12 +2126,55 @@ func simdAMD64Ops(v11, v21, v2k, vkv, v2kv, v2kk, v31, v3kv, vgpv, vgp, vfpv, vf
|
||||
{name: "VBROADCASTSSMasked128Merging", argLength: 3, reg: w2kw, asm: "VBROADCASTSS", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VBROADCASTSSMasked256Merging", argLength: 3, reg: w2kw, asm: "VBROADCASTSS", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VBROADCASTSSMasked512Merging", argLength: 3, reg: w2kw, asm: "VBROADCASTSS", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VCVTPS2UDQMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTPS2UDQ", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VCVTPS2UDQMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTPS2UDQ", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VCVTPS2UDQMasked512Merging", argLength: 3, reg: w2kw, asm: "VCVTPS2UDQ", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VCVTDQ2PDMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTDQ2PD", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VCVTDQ2PDMasked512Merging", argLength: 3, reg: w2kw, asm: "VCVTDQ2PD", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VCVTDQ2PSMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTDQ2PS", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VCVTDQ2PSMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTDQ2PS", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VCVTDQ2PSMasked512Merging", argLength: 3, reg: w2kw, asm: "VCVTDQ2PS", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VCVTPD2PSMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTPD2PS", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VCVTPD2PSXMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTPD2PSX", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VCVTPD2PSYMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTPD2PSY", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VCVTPS2PDMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTPS2PD", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VCVTPS2PDMasked512Merging", argLength: 3, reg: w2kw, asm: "VCVTPS2PD", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VCVTQQ2PDMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTQQ2PD", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VCVTQQ2PDMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTQQ2PD", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VCVTQQ2PDMasked512Merging", argLength: 3, reg: w2kw, asm: "VCVTQQ2PD", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VCVTQQ2PSMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTQQ2PS", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VCVTQQ2PSXMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTQQ2PSX", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VCVTQQ2PSYMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTQQ2PSY", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VCVTTPD2DQMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTTPD2DQ", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VCVTTPD2DQXMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTTPD2DQX", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VCVTTPD2DQYMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTTPD2DQY", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VCVTTPD2QQMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTTPD2QQ", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VCVTTPD2QQMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTTPD2QQ", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VCVTTPD2QQMasked512Merging", argLength: 3, reg: w2kw, asm: "VCVTTPD2QQ", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VCVTTPD2UDQMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTTPD2UDQ", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VCVTTPD2UDQXMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTTPD2UDQX", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VCVTTPD2UDQYMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTTPD2UDQY", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VCVTTPD2UQQMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTTPD2UQQ", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VCVTTPD2UQQMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTTPD2UQQ", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VCVTTPD2UQQMasked512Merging", argLength: 3, reg: w2kw, asm: "VCVTTPD2UQQ", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VCVTTPS2DQMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTTPS2DQ", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VCVTTPS2DQMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTTPS2DQ", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VCVTTPS2DQMasked512Merging", argLength: 3, reg: w2kw, asm: "VCVTTPS2DQ", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VCVTTPS2QQMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTTPS2QQ", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VCVTTPS2QQMasked512Merging", argLength: 3, reg: w2kw, asm: "VCVTTPS2QQ", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VCVTTPS2UDQMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTTPS2UDQ", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VCVTTPS2UDQMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTTPS2UDQ", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VCVTTPS2UDQMasked512Merging", argLength: 3, reg: w2kw, asm: "VCVTTPS2UDQ", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VCVTTPS2UQQMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTTPS2UQQ", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VCVTTPS2UQQMasked512Merging", argLength: 3, reg: w2kw, asm: "VCVTTPS2UQQ", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VCVTUDQ2PDMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTUDQ2PD", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VCVTUDQ2PDMasked512Merging", argLength: 3, reg: w2kw, asm: "VCVTUDQ2PD", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VCVTUDQ2PSMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTUDQ2PS", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VCVTUDQ2PSMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTUDQ2PS", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VCVTUDQ2PSMasked512Merging", argLength: 3, reg: w2kw, asm: "VCVTUDQ2PS", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VCVTUQQ2PDMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTUQQ2PD", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VCVTUQQ2PDMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTUQQ2PD", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VCVTUQQ2PDMasked512Merging", argLength: 3, reg: w2kw, asm: "VCVTUQQ2PD", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VCVTUQQ2PSMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTUQQ2PS", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VCVTUQQ2PSXMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTUQQ2PSX", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VCVTUQQ2PSYMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTUQQ2PSY", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VDIVPDMasked128Merging", argLength: 4, reg: w3kw, asm: "VDIVPD", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VDIVPDMasked256Merging", argLength: 4, reg: w3kw, asm: "VDIVPD", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VDIVPDMasked512Merging", argLength: 4, reg: w3kw, asm: "VDIVPD", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
|
||||
@ -237,12 +237,55 @@ func simdGenericOps() []opData {
|
||||
{name: "ConcatPermuteUint64x2", argLength: 3, commutative: false},
|
||||
{name: "ConcatPermuteUint64x4", argLength: 3, commutative: false},
|
||||
{name: "ConcatPermuteUint64x8", argLength: 3, commutative: false},
|
||||
{name: "ConvertToFloat32Float64x2", argLength: 1, commutative: false},
|
||||
{name: "ConvertToFloat32Float64x4", argLength: 1, commutative: false},
|
||||
{name: "ConvertToFloat32Float64x8", argLength: 1, commutative: false},
|
||||
{name: "ConvertToFloat32Int32x4", argLength: 1, commutative: false},
|
||||
{name: "ConvertToFloat32Int32x8", argLength: 1, commutative: false},
|
||||
{name: "ConvertToFloat32Int32x16", argLength: 1, commutative: false},
|
||||
{name: "ConvertToFloat32Int64x2", argLength: 1, commutative: false},
|
||||
{name: "ConvertToFloat32Int64x4", argLength: 1, commutative: false},
|
||||
{name: "ConvertToFloat32Int64x8", argLength: 1, commutative: false},
|
||||
{name: "ConvertToFloat32Uint32x4", argLength: 1, commutative: false},
|
||||
{name: "ConvertToFloat32Uint32x8", argLength: 1, commutative: false},
|
||||
{name: "ConvertToFloat32Uint32x16", argLength: 1, commutative: false},
|
||||
{name: "ConvertToFloat32Uint64x2", argLength: 1, commutative: false},
|
||||
{name: "ConvertToFloat32Uint64x4", argLength: 1, commutative: false},
|
||||
{name: "ConvertToFloat32Uint64x8", argLength: 1, commutative: false},
|
||||
{name: "ConvertToFloat64Float32x4", argLength: 1, commutative: false},
|
||||
{name: "ConvertToFloat64Float32x8", argLength: 1, commutative: false},
|
||||
{name: "ConvertToFloat64Int32x4", argLength: 1, commutative: false},
|
||||
{name: "ConvertToFloat64Int32x8", argLength: 1, commutative: false},
|
||||
{name: "ConvertToFloat64Int64x2", argLength: 1, commutative: false},
|
||||
{name: "ConvertToFloat64Int64x4", argLength: 1, commutative: false},
|
||||
{name: "ConvertToFloat64Int64x8", argLength: 1, commutative: false},
|
||||
{name: "ConvertToFloat64Uint32x4", argLength: 1, commutative: false},
|
||||
{name: "ConvertToFloat64Uint32x8", argLength: 1, commutative: false},
|
||||
{name: "ConvertToFloat64Uint64x2", argLength: 1, commutative: false},
|
||||
{name: "ConvertToFloat64Uint64x4", argLength: 1, commutative: false},
|
||||
{name: "ConvertToFloat64Uint64x8", argLength: 1, commutative: false},
|
||||
{name: "ConvertToInt32Float32x4", argLength: 1, commutative: false},
|
||||
{name: "ConvertToInt32Float32x8", argLength: 1, commutative: false},
|
||||
{name: "ConvertToInt32Float32x16", argLength: 1, commutative: false},
|
||||
{name: "ConvertToInt32Float64x2", argLength: 1, commutative: false},
|
||||
{name: "ConvertToInt32Float64x4", argLength: 1, commutative: false},
|
||||
{name: "ConvertToInt32Float64x8", argLength: 1, commutative: false},
|
||||
{name: "ConvertToInt64Float32x4", argLength: 1, commutative: false},
|
||||
{name: "ConvertToInt64Float32x8", argLength: 1, commutative: false},
|
||||
{name: "ConvertToInt64Float64x2", argLength: 1, commutative: false},
|
||||
{name: "ConvertToInt64Float64x4", argLength: 1, commutative: false},
|
||||
{name: "ConvertToInt64Float64x8", argLength: 1, commutative: false},
|
||||
{name: "ConvertToUint32Float32x4", argLength: 1, commutative: false},
|
||||
{name: "ConvertToUint32Float32x8", argLength: 1, commutative: false},
|
||||
{name: "ConvertToUint32Float32x16", argLength: 1, commutative: false},
|
||||
{name: "ConvertToUint32Float64x2", argLength: 1, commutative: false},
|
||||
{name: "ConvertToUint32Float64x4", argLength: 1, commutative: false},
|
||||
{name: "ConvertToUint32Float64x8", argLength: 1, commutative: false},
|
||||
{name: "ConvertToUint64Float32x4", argLength: 1, commutative: false},
|
||||
{name: "ConvertToUint64Float32x8", argLength: 1, commutative: false},
|
||||
{name: "ConvertToUint64Float64x2", argLength: 1, commutative: false},
|
||||
{name: "ConvertToUint64Float64x4", argLength: 1, commutative: false},
|
||||
{name: "ConvertToUint64Float64x8", argLength: 1, commutative: false},
|
||||
{name: "CopySignInt8x16", argLength: 2, commutative: false},
|
||||
{name: "CopySignInt8x32", argLength: 2, commutative: false},
|
||||
{name: "CopySignInt16x8", argLength: 2, commutative: false},
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -261,12 +261,55 @@ func simdIntrinsics(addF func(pkg, fn string, b intrinsicBuilder, archFamilies .
|
||||
addF(simdPackage, "Uint8x16.ConcatShiftBytesRight", opLen2Imm8(ssa.OpConcatShiftBytesRightUint8x16, types.TypeVec128, 0), sys.AMD64)
|
||||
addF(simdPackage, "Uint8x32.ConcatShiftBytesRightGrouped", opLen2Imm8(ssa.OpConcatShiftBytesRightGroupedUint8x32, types.TypeVec256, 0), sys.AMD64)
|
||||
addF(simdPackage, "Uint8x64.ConcatShiftBytesRightGrouped", opLen2Imm8(ssa.OpConcatShiftBytesRightGroupedUint8x64, types.TypeVec512, 0), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.ConvertToFloat32", opLen1(ssa.OpConvertToFloat32Float64x2, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.ConvertToFloat32", opLen1(ssa.OpConvertToFloat32Float64x4, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.ConvertToFloat32", opLen1(ssa.OpConvertToFloat32Float64x8, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Int32x4.ConvertToFloat32", opLen1(ssa.OpConvertToFloat32Int32x4, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Int32x8.ConvertToFloat32", opLen1(ssa.OpConvertToFloat32Int32x8, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Int32x16.ConvertToFloat32", opLen1(ssa.OpConvertToFloat32Int32x16, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Int64x2.ConvertToFloat32", opLen1(ssa.OpConvertToFloat32Int64x2, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Int64x4.ConvertToFloat32", opLen1(ssa.OpConvertToFloat32Int64x4, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Int64x8.ConvertToFloat32", opLen1(ssa.OpConvertToFloat32Int64x8, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Uint32x4.ConvertToFloat32", opLen1(ssa.OpConvertToFloat32Uint32x4, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Uint32x8.ConvertToFloat32", opLen1(ssa.OpConvertToFloat32Uint32x8, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Uint32x16.ConvertToFloat32", opLen1(ssa.OpConvertToFloat32Uint32x16, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Uint64x2.ConvertToFloat32", opLen1(ssa.OpConvertToFloat32Uint64x2, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Uint64x4.ConvertToFloat32", opLen1(ssa.OpConvertToFloat32Uint64x4, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Uint64x8.ConvertToFloat32", opLen1(ssa.OpConvertToFloat32Uint64x8, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.ConvertToFloat64", opLen1(ssa.OpConvertToFloat64Float32x4, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.ConvertToFloat64", opLen1(ssa.OpConvertToFloat64Float32x8, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Int32x4.ConvertToFloat64", opLen1(ssa.OpConvertToFloat64Int32x4, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Int32x8.ConvertToFloat64", opLen1(ssa.OpConvertToFloat64Int32x8, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Int64x2.ConvertToFloat64", opLen1(ssa.OpConvertToFloat64Int64x2, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Int64x4.ConvertToFloat64", opLen1(ssa.OpConvertToFloat64Int64x4, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Int64x8.ConvertToFloat64", opLen1(ssa.OpConvertToFloat64Int64x8, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Uint32x4.ConvertToFloat64", opLen1(ssa.OpConvertToFloat64Uint32x4, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Uint32x8.ConvertToFloat64", opLen1(ssa.OpConvertToFloat64Uint32x8, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Uint64x2.ConvertToFloat64", opLen1(ssa.OpConvertToFloat64Uint64x2, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Uint64x4.ConvertToFloat64", opLen1(ssa.OpConvertToFloat64Uint64x4, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Uint64x8.ConvertToFloat64", opLen1(ssa.OpConvertToFloat64Uint64x8, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.ConvertToInt32", opLen1(ssa.OpConvertToInt32Float32x4, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.ConvertToInt32", opLen1(ssa.OpConvertToInt32Float32x8, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.ConvertToInt32", opLen1(ssa.OpConvertToInt32Float32x16, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.ConvertToInt32", opLen1(ssa.OpConvertToInt32Float64x2, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.ConvertToInt32", opLen1(ssa.OpConvertToInt32Float64x4, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.ConvertToInt32", opLen1(ssa.OpConvertToInt32Float64x8, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.ConvertToInt64", opLen1(ssa.OpConvertToInt64Float32x4, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.ConvertToInt64", opLen1(ssa.OpConvertToInt64Float32x8, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.ConvertToInt64", opLen1(ssa.OpConvertToInt64Float64x2, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.ConvertToInt64", opLen1(ssa.OpConvertToInt64Float64x4, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.ConvertToInt64", opLen1(ssa.OpConvertToInt64Float64x8, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.ConvertToUint32", opLen1(ssa.OpConvertToUint32Float32x4, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.ConvertToUint32", opLen1(ssa.OpConvertToUint32Float32x8, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.ConvertToUint32", opLen1(ssa.OpConvertToUint32Float32x16, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.ConvertToUint32", opLen1(ssa.OpConvertToUint32Float64x2, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.ConvertToUint32", opLen1(ssa.OpConvertToUint32Float64x4, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.ConvertToUint32", opLen1(ssa.OpConvertToUint32Float64x8, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.ConvertToUint64", opLen1(ssa.OpConvertToUint64Float32x4, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.ConvertToUint64", opLen1(ssa.OpConvertToUint64Float32x8, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.ConvertToUint64", opLen1(ssa.OpConvertToUint64Float64x2, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.ConvertToUint64", opLen1(ssa.OpConvertToUint64Float64x4, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.ConvertToUint64", opLen1(ssa.OpConvertToUint64Float64x8, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Int8x16.CopySign", opLen2(ssa.OpCopySignInt8x16, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Int8x32.CopySign", opLen2(ssa.OpCopySignInt8x32, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Int16x8.CopySign", opLen2(ssa.OpCopySignInt16x8, types.TypeVec128), sys.AMD64)
|
||||
|
||||
@ -98,6 +98,10 @@ func writeSIMDMachineOps(ops []Operation) *bytes.Buffer {
|
||||
mOpOrder = append(mOpOrder, asm)
|
||||
continue
|
||||
}
|
||||
if !op.Commutative && other.Commutative { // if there's a non-commutative version of the op, it wins.
|
||||
best[asm] = op
|
||||
continue
|
||||
}
|
||||
// see if "op" is better than "other"
|
||||
if countOverrides(op.In)+countOverrides(op.Out) < countOverrides(other.In)+countOverrides(other.Out) {
|
||||
best[asm] = op
|
||||
|
||||
@ -322,7 +322,7 @@ func writeSIMDRules(ops []Operation) *bytes.Buffer {
|
||||
rule := fmt.Sprintf("(VPBLENDVB%d dst (%s %s) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (%sMerging dst %s (VPMOVVec%dx%dToM <types.TypeMask> mask))\n",
|
||||
*maskElem.Bits, noMaskName, data.Args, data.Asm, data.Args, *maskElem.ElemBits, *maskElem.Lanes)
|
||||
if ok && ruleExisting != rule {
|
||||
panic("multiple masked merge rules for one op")
|
||||
panic(fmt.Sprintf("multiple masked merge rules for one op:\n%s\n%s\n", ruleExisting, rule))
|
||||
} else {
|
||||
maskedMergeOpts[noMaskName] = rule
|
||||
}
|
||||
@ -333,7 +333,7 @@ func writeSIMDRules(ops []Operation) *bytes.Buffer {
|
||||
rule := fmt.Sprintf("(VPBLENDM%sMasked%d dst (%s %s) mask) => (%sMerging dst %s mask)\n",
|
||||
s2n[*maskElem.ElemBits], *maskElem.Bits, noMaskName, data.Args, data.Asm, data.Args)
|
||||
if ok && ruleExisting != rule {
|
||||
panic("multiple masked merge rules for one op")
|
||||
panic(fmt.Sprintf("multiple masked merge rules for one op:\n%s\n%s\n", ruleExisting, rule))
|
||||
} else {
|
||||
maskedMergeOpts[noMaskName] = rule
|
||||
}
|
||||
|
||||
@ -335,6 +335,20 @@ func (op *Operation) sortOperand() {
|
||||
})
|
||||
}
|
||||
|
||||
// adjustAsm adjusts the asm to make it align with Go's assembler.
|
||||
func (op *Operation) adjustAsm() {
|
||||
if op.Asm == "VCVTTPD2DQ" || op.Asm == "VCVTTPD2UDQ" ||
|
||||
op.Asm == "VCVTQQ2PS" || op.Asm == "VCVTUQQ2PS" ||
|
||||
op.Asm == "VCVTPD2PS" {
|
||||
switch *op.In[0].Bits {
|
||||
case 128:
|
||||
op.Asm += "X"
|
||||
case 256:
|
||||
op.Asm += "Y"
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// goNormalType returns the Go type name for the result of an Op that
|
||||
// does not return a vector, i.e., that returns a result in a general
|
||||
// register. Currently there's only one family of Ops in Go's simd library
|
||||
@ -652,6 +666,12 @@ func dedupGodef(ops []Operation) ([]Operation, error) {
|
||||
if i.MemFeatures == nil && j.MemFeatures != nil {
|
||||
return 1
|
||||
}
|
||||
if i.Commutative != j.Commutative {
|
||||
if j.Commutative {
|
||||
return -1
|
||||
}
|
||||
return 1
|
||||
}
|
||||
// Their order does not matter anymore, at least for now.
|
||||
return 0
|
||||
})
|
||||
|
||||
@ -381,6 +381,7 @@ func writeGoDefs(path string, cl unify.Closure) error {
|
||||
}
|
||||
// TODO: verify that this is safe.
|
||||
op.sortOperand()
|
||||
op.adjustAsm()
|
||||
ops = append(ops, op)
|
||||
}
|
||||
slices.SortFunc(ops, compareOperations)
|
||||
@ -399,9 +400,6 @@ func writeGoDefs(path string, cl unify.Closure) error {
|
||||
if *Verbose {
|
||||
log.Printf("dedup len: %d\n", len(deduped))
|
||||
}
|
||||
if *Verbose {
|
||||
log.Printf("dedup len: %d\n", len(deduped))
|
||||
}
|
||||
if !*FlagNoDedup {
|
||||
// TODO: This can hide mistakes in the API definitions, especially when
|
||||
// multiple patterns result in the same API unintentionally. Make it stricter.
|
||||
|
||||
@ -10,17 +10,17 @@
|
||||
constImm: 0
|
||||
commutative: true
|
||||
documentation: !string |-
|
||||
// NAME compares for equality.
|
||||
// NAME returns x equals y, elementwise.
|
||||
- go: Less
|
||||
constImm: 1
|
||||
commutative: false
|
||||
documentation: !string |-
|
||||
// NAME compares for less than.
|
||||
// NAME returns x less-than y, elementwise.
|
||||
- go: LessEqual
|
||||
constImm: 2
|
||||
commutative: false
|
||||
documentation: !string |-
|
||||
// NAME compares for less than or equal.
|
||||
// NAME returns x less-than-or-equals y, elementwise.
|
||||
- go: IsNan # For float only.
|
||||
constImm: 3
|
||||
commutative: true
|
||||
@ -30,14 +30,14 @@
|
||||
constImm: 4
|
||||
commutative: true
|
||||
documentation: !string |-
|
||||
// NAME compares for inequality.
|
||||
// NAME returns x not-equals y, elementwise.
|
||||
- go: GreaterEqual
|
||||
constImm: 13
|
||||
commutative: false
|
||||
documentation: !string |-
|
||||
// NAME compares for greater than or equal.
|
||||
// NAME returns x greater-than-or-equals y, elementwise.
|
||||
- go: Greater
|
||||
constImm: 14
|
||||
commutative: false
|
||||
documentation: !string |-
|
||||
// NAME compares for greater than.
|
||||
// NAME returns x greater-than y, elementwise.
|
||||
|
||||
@ -1,6 +1,49 @@
|
||||
!sum
|
||||
# Non-truncating conversions
|
||||
# int<->int or uint<->uint widening, float<->int|uint conversions or trucating conversions.
|
||||
# Float <-> Int conversions
|
||||
- go: "ConvertToInt32"
|
||||
commutative: false
|
||||
regexpTag: "convert"
|
||||
documentation: !string |-
|
||||
// NAME converts element values to int32.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result cannot be represented in int32, an implementation-defined
|
||||
// architecture-specific value is returned.
|
||||
- go: "ConvertToUint32"
|
||||
commutative: false
|
||||
regexpTag: "convert"
|
||||
documentation: !string |-
|
||||
// NAME converts element values to uint32.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result cannot be represented in uint32, an implementation-defined
|
||||
// architecture-specific value is returned.
|
||||
- go: "ConvertToInt64"
|
||||
commutative: false
|
||||
regexpTag: "convert"
|
||||
documentation: !string |-
|
||||
// NAME converts element values to int64.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result cannot be represented in int64, an implementation-defined
|
||||
// architecture-specific value is returned.
|
||||
- go: "ConvertToUint64"
|
||||
commutative: false
|
||||
regexpTag: "convert"
|
||||
documentation: !string |-
|
||||
// NAME converts element values to uint64.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result cannot be represented in uint64, an implementation-defined
|
||||
// architecture-specific value is returned.
|
||||
- go: "ConvertToFloat32" # Also float64 -> float32
|
||||
commutative: false
|
||||
regexpTag: "convert"
|
||||
documentation: !string |-
|
||||
// NAME converts element values to float32.
|
||||
- go: "ConvertToFloat64" # Also float32 -> float64
|
||||
commutative: false
|
||||
regexpTag: "convert"
|
||||
documentation: !string |-
|
||||
// NAME converts element values to float64.
|
||||
|
||||
# Int <-> Int conversions
|
||||
- go: "(Extend|Saturate|Truncate)?ToInt8"
|
||||
commutative: false
|
||||
regexpTag: "convert"
|
||||
@ -11,7 +54,7 @@
|
||||
regexpTag: "convert"
|
||||
documentation: !string |-
|
||||
// NAME converts element values to int16.
|
||||
- go: "(Extend|Saturate|Truncate)?(Convert)?ToInt32"
|
||||
- go: "(Extend|Saturate|Truncate)?ToInt32"
|
||||
commutative: false
|
||||
regexpTag: "convert"
|
||||
documentation: !string |-
|
||||
@ -31,7 +74,7 @@
|
||||
regexpTag: "convert"
|
||||
documentation: !string |-
|
||||
// NAME converts element values to uint16.
|
||||
- go: "(Extend|Saturate|Truncate)?(Convert)?ToUint32"
|
||||
- go: "(Extend|Saturate|Truncate)?ToUint32"
|
||||
regexpTag: "convert"
|
||||
commutative: false
|
||||
documentation: !string |-
|
||||
@ -41,9 +84,7 @@
|
||||
commutative: false
|
||||
documentation: !string |-
|
||||
// NAME converts element values to uint64.
|
||||
|
||||
# low-part only conversions
|
||||
# int<->int or uint<->uint widening conversions.
|
||||
# low-part only Int <-> Int conversions
|
||||
- go: ExtendLo8ToUint16x8
|
||||
commutative: false
|
||||
documentation: !string |-
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
# float32 -> int32
|
||||
- go: ConvertToInt32
|
||||
regexpTag: "convert"
|
||||
asm: "VCVTTPS2DQ"
|
||||
asm: "VCVTTP[SD]2DQ"
|
||||
in:
|
||||
- &fp
|
||||
go: $t
|
||||
@ -16,7 +16,7 @@
|
||||
# float32 -> uint32
|
||||
- go: ConvertToUint32
|
||||
regexpTag: "convert"
|
||||
asm: "VCVTPS2UDQ"
|
||||
asm: "VCVTTP[SD]2UDQ"
|
||||
in:
|
||||
- *fp
|
||||
out:
|
||||
@ -24,6 +24,117 @@
|
||||
go: $u
|
||||
base: uint
|
||||
elemBits: 32
|
||||
# float32|float64 -> int64
|
||||
- go: ConvertToInt64
|
||||
regexpTag: "convert"
|
||||
asm: "VCVTTPD2QQ"
|
||||
in:
|
||||
- *fp
|
||||
out:
|
||||
- &i64
|
||||
go: $u
|
||||
base: int
|
||||
elemBits: 64
|
||||
- go: ConvertToInt64
|
||||
regexpTag: "convert"
|
||||
asm: "VCVTTPS2QQ"
|
||||
in:
|
||||
- *fp
|
||||
out:
|
||||
- go: $u
|
||||
base: int
|
||||
elemBits: 64
|
||||
bits: 256|512
|
||||
# float32|float64 -> uint64
|
||||
- go: ConvertToUint64
|
||||
regexpTag: "convert"
|
||||
asm: "VCVTTPD2UQQ"
|
||||
in:
|
||||
- *fp
|
||||
out:
|
||||
- &u64
|
||||
go: $u
|
||||
base: uint
|
||||
elemBits: 64
|
||||
- go: ConvertToUint64
|
||||
regexpTag: "convert"
|
||||
asm: "VCVTTPS2UQQ"
|
||||
in:
|
||||
- *fp
|
||||
out:
|
||||
- go: $u
|
||||
base: uint
|
||||
elemBits: 64
|
||||
bits: 256|512
|
||||
# int -> float32
|
||||
- go: ConvertToFloat32
|
||||
regexpTag: "convert"
|
||||
asm: "VCVT[DQ]Q2PS"
|
||||
in: &int
|
||||
- go: $i
|
||||
base: int
|
||||
out:
|
||||
- *fp
|
||||
# int -> float64
|
||||
- go: ConvertToFloat64
|
||||
regexpTag: "convert"
|
||||
asm: "VCVTQQ2PD"
|
||||
in: *int
|
||||
out:
|
||||
- *fp
|
||||
- go: ConvertToFloat64
|
||||
regexpTag: "convert"
|
||||
asm: "VCVTDQ2PD"
|
||||
in: *int
|
||||
out:
|
||||
- base: float
|
||||
bits: 256|512
|
||||
# uint -> float32
|
||||
- go: ConvertToFloat32
|
||||
regexpTag: "convert"
|
||||
asm: "VCVTU[DQ]Q2PS"
|
||||
in: &uint
|
||||
- go: $u
|
||||
base: uint
|
||||
out:
|
||||
- *fp
|
||||
# uint -> float64
|
||||
- go: ConvertToFloat64
|
||||
regexpTag: "convert"
|
||||
asm: "VCVTUQQ2PD"
|
||||
in: *uint
|
||||
out:
|
||||
- *fp
|
||||
- go: ConvertToFloat64
|
||||
regexpTag: "convert"
|
||||
asm: "VCVTUDQ2PD"
|
||||
in: *uint
|
||||
out:
|
||||
- base: float
|
||||
bits: 256|512
|
||||
# float64 -> float32
|
||||
- go: ConvertToFloat32
|
||||
regexpTag: "convert"
|
||||
asm: "VCVTPD2PS"
|
||||
addDoc:
|
||||
!string |-
|
||||
// The result vector's elements are rounded to the nearest value.
|
||||
in: &fp64
|
||||
- base: float
|
||||
elemBits: 64
|
||||
out: &fp32
|
||||
- base: float
|
||||
elemBits: 32
|
||||
# float32 -> float64
|
||||
- go: ConvertToFloat64
|
||||
regexpTag: "convert"
|
||||
asm: "VCVTPS2PD"
|
||||
in: *fp32
|
||||
out:
|
||||
- base: float
|
||||
elemBits: 64
|
||||
bits: 256|512
|
||||
|
||||
# Widening integer conversions.
|
||||
# uint8 -> uint16
|
||||
- go: ExtendToUint16
|
||||
|
||||
@ -1544,40 +1544,332 @@ func (x Uint8x32) ConcatShiftBytesRightGrouped(constant uint8, y Uint8x32) Uint8
|
||||
// Asm: VPALIGNR, CPU Feature: AVX512
|
||||
func (x Uint8x64) ConcatShiftBytesRightGrouped(constant uint8, y Uint8x64) Uint8x64
|
||||
|
||||
/* ConvertToFloat32 */
|
||||
|
||||
// ConvertToFloat32 converts element values to float32.
|
||||
// The result vector's elements are rounded to the nearest value.
|
||||
//
|
||||
// Asm: VCVTPD2PSX, CPU Feature: AVX
|
||||
func (x Float64x2) ConvertToFloat32() Float32x4
|
||||
|
||||
// ConvertToFloat32 converts element values to float32.
|
||||
// The result vector's elements are rounded to the nearest value.
|
||||
//
|
||||
// Asm: VCVTPD2PSY, CPU Feature: AVX
|
||||
func (x Float64x4) ConvertToFloat32() Float32x4
|
||||
|
||||
// ConvertToFloat32 converts element values to float32.
|
||||
// The result vector's elements are rounded to the nearest value.
|
||||
//
|
||||
// Asm: VCVTPD2PS, CPU Feature: AVX512
|
||||
func (x Float64x8) ConvertToFloat32() Float32x8
|
||||
|
||||
// ConvertToFloat32 converts element values to float32.
|
||||
//
|
||||
// Asm: VCVTDQ2PS, CPU Feature: AVX
|
||||
func (x Int32x4) ConvertToFloat32() Float32x4
|
||||
|
||||
// ConvertToFloat32 converts element values to float32.
|
||||
//
|
||||
// Asm: VCVTDQ2PS, CPU Feature: AVX
|
||||
func (x Int32x8) ConvertToFloat32() Float32x8
|
||||
|
||||
// ConvertToFloat32 converts element values to float32.
|
||||
//
|
||||
// Asm: VCVTDQ2PS, CPU Feature: AVX512
|
||||
func (x Int32x16) ConvertToFloat32() Float32x16
|
||||
|
||||
// ConvertToFloat32 converts element values to float32.
|
||||
//
|
||||
// Asm: VCVTQQ2PSX, CPU Feature: AVX512
|
||||
func (x Int64x2) ConvertToFloat32() Float32x4
|
||||
|
||||
// ConvertToFloat32 converts element values to float32.
|
||||
//
|
||||
// Asm: VCVTQQ2PSY, CPU Feature: AVX512
|
||||
func (x Int64x4) ConvertToFloat32() Float32x4
|
||||
|
||||
// ConvertToFloat32 converts element values to float32.
|
||||
//
|
||||
// Asm: VCVTQQ2PS, CPU Feature: AVX512
|
||||
func (x Int64x8) ConvertToFloat32() Float32x8
|
||||
|
||||
// ConvertToFloat32 converts element values to float32.
|
||||
//
|
||||
// Asm: VCVTUDQ2PS, CPU Feature: AVX512
|
||||
func (x Uint32x4) ConvertToFloat32() Float32x4
|
||||
|
||||
// ConvertToFloat32 converts element values to float32.
|
||||
//
|
||||
// Asm: VCVTUDQ2PS, CPU Feature: AVX512
|
||||
func (x Uint32x8) ConvertToFloat32() Float32x8
|
||||
|
||||
// ConvertToFloat32 converts element values to float32.
|
||||
//
|
||||
// Asm: VCVTUDQ2PS, CPU Feature: AVX512
|
||||
func (x Uint32x16) ConvertToFloat32() Float32x16
|
||||
|
||||
// ConvertToFloat32 converts element values to float32.
|
||||
//
|
||||
// Asm: VCVTUQQ2PSX, CPU Feature: AVX512
|
||||
func (x Uint64x2) ConvertToFloat32() Float32x4
|
||||
|
||||
// ConvertToFloat32 converts element values to float32.
|
||||
//
|
||||
// Asm: VCVTUQQ2PSY, CPU Feature: AVX512
|
||||
func (x Uint64x4) ConvertToFloat32() Float32x4
|
||||
|
||||
// ConvertToFloat32 converts element values to float32.
|
||||
//
|
||||
// Asm: VCVTUQQ2PS, CPU Feature: AVX512
|
||||
func (x Uint64x8) ConvertToFloat32() Float32x8
|
||||
|
||||
/* ConvertToFloat64 */
|
||||
|
||||
// ConvertToFloat64 converts element values to float64.
|
||||
//
|
||||
// Asm: VCVTPS2PD, CPU Feature: AVX
|
||||
func (x Float32x4) ConvertToFloat64() Float64x4
|
||||
|
||||
// ConvertToFloat64 converts element values to float64.
|
||||
//
|
||||
// Asm: VCVTPS2PD, CPU Feature: AVX512
|
||||
func (x Float32x8) ConvertToFloat64() Float64x8
|
||||
|
||||
// ConvertToFloat64 converts element values to float64.
|
||||
//
|
||||
// Asm: VCVTDQ2PD, CPU Feature: AVX
|
||||
func (x Int32x4) ConvertToFloat64() Float64x4
|
||||
|
||||
// ConvertToFloat64 converts element values to float64.
|
||||
//
|
||||
// Asm: VCVTDQ2PD, CPU Feature: AVX512
|
||||
func (x Int32x8) ConvertToFloat64() Float64x8
|
||||
|
||||
// ConvertToFloat64 converts element values to float64.
|
||||
//
|
||||
// Asm: VCVTQQ2PD, CPU Feature: AVX512
|
||||
func (x Int64x2) ConvertToFloat64() Float64x2
|
||||
|
||||
// ConvertToFloat64 converts element values to float64.
|
||||
//
|
||||
// Asm: VCVTQQ2PD, CPU Feature: AVX512
|
||||
func (x Int64x4) ConvertToFloat64() Float64x4
|
||||
|
||||
// ConvertToFloat64 converts element values to float64.
|
||||
//
|
||||
// Asm: VCVTQQ2PD, CPU Feature: AVX512
|
||||
func (x Int64x8) ConvertToFloat64() Float64x8
|
||||
|
||||
// ConvertToFloat64 converts element values to float64.
|
||||
//
|
||||
// Asm: VCVTUDQ2PD, CPU Feature: AVX512
|
||||
func (x Uint32x4) ConvertToFloat64() Float64x4
|
||||
|
||||
// ConvertToFloat64 converts element values to float64.
|
||||
//
|
||||
// Asm: VCVTUDQ2PD, CPU Feature: AVX512
|
||||
func (x Uint32x8) ConvertToFloat64() Float64x8
|
||||
|
||||
// ConvertToFloat64 converts element values to float64.
|
||||
//
|
||||
// Asm: VCVTUQQ2PD, CPU Feature: AVX512
|
||||
func (x Uint64x2) ConvertToFloat64() Float64x2
|
||||
|
||||
// ConvertToFloat64 converts element values to float64.
|
||||
//
|
||||
// Asm: VCVTUQQ2PD, CPU Feature: AVX512
|
||||
func (x Uint64x4) ConvertToFloat64() Float64x4
|
||||
|
||||
// ConvertToFloat64 converts element values to float64.
|
||||
//
|
||||
// Asm: VCVTUQQ2PD, CPU Feature: AVX512
|
||||
func (x Uint64x8) ConvertToFloat64() Float64x8
|
||||
|
||||
/* ConvertToInt32 */
|
||||
|
||||
// ConvertToInt32 converts element values to int32.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result cannot be represented in int32, an implementation-defined
|
||||
// architecture-specific value is returned.
|
||||
//
|
||||
// Asm: VCVTTPS2DQ, CPU Feature: AVX
|
||||
func (x Float32x4) ConvertToInt32() Int32x4
|
||||
|
||||
// ConvertToInt32 converts element values to int32.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result cannot be represented in int32, an implementation-defined
|
||||
// architecture-specific value is returned.
|
||||
//
|
||||
// Asm: VCVTTPS2DQ, CPU Feature: AVX
|
||||
func (x Float32x8) ConvertToInt32() Int32x8
|
||||
|
||||
// ConvertToInt32 converts element values to int32.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result cannot be represented in int32, an implementation-defined
|
||||
// architecture-specific value is returned.
|
||||
//
|
||||
// Asm: VCVTTPS2DQ, CPU Feature: AVX512
|
||||
func (x Float32x16) ConvertToInt32() Int32x16
|
||||
|
||||
// ConvertToInt32 converts element values to int32.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result cannot be represented in int32, an implementation-defined
|
||||
// architecture-specific value is returned.
|
||||
//
|
||||
// Asm: VCVTTPD2DQX, CPU Feature: AVX
|
||||
func (x Float64x2) ConvertToInt32() Int32x4
|
||||
|
||||
// ConvertToInt32 converts element values to int32.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result cannot be represented in int32, an implementation-defined
|
||||
// architecture-specific value is returned.
|
||||
//
|
||||
// Asm: VCVTTPD2DQY, CPU Feature: AVX
|
||||
func (x Float64x4) ConvertToInt32() Int32x4
|
||||
|
||||
// ConvertToInt32 converts element values to int32.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result cannot be represented in int32, an implementation-defined
|
||||
// architecture-specific value is returned.
|
||||
//
|
||||
// Asm: VCVTTPD2DQ, CPU Feature: AVX512
|
||||
func (x Float64x8) ConvertToInt32() Int32x8
|
||||
|
||||
/* ConvertToInt64 */
|
||||
|
||||
// ConvertToInt64 converts element values to int64.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result cannot be represented in int64, an implementation-defined
|
||||
// architecture-specific value is returned.
|
||||
//
|
||||
// Asm: VCVTTPS2QQ, CPU Feature: AVX512
|
||||
func (x Float32x4) ConvertToInt64() Int64x4
|
||||
|
||||
// ConvertToInt64 converts element values to int64.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result cannot be represented in int64, an implementation-defined
|
||||
// architecture-specific value is returned.
|
||||
//
|
||||
// Asm: VCVTTPS2QQ, CPU Feature: AVX512
|
||||
func (x Float32x8) ConvertToInt64() Int64x8
|
||||
|
||||
// ConvertToInt64 converts element values to int64.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result cannot be represented in int64, an implementation-defined
|
||||
// architecture-specific value is returned.
|
||||
//
|
||||
// Asm: VCVTTPD2QQ, CPU Feature: AVX512
|
||||
func (x Float64x2) ConvertToInt64() Int64x2
|
||||
|
||||
// ConvertToInt64 converts element values to int64.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result cannot be represented in int64, an implementation-defined
|
||||
// architecture-specific value is returned.
|
||||
//
|
||||
// Asm: VCVTTPD2QQ, CPU Feature: AVX512
|
||||
func (x Float64x4) ConvertToInt64() Int64x4
|
||||
|
||||
// ConvertToInt64 converts element values to int64.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result cannot be represented in int64, an implementation-defined
|
||||
// architecture-specific value is returned.
|
||||
//
|
||||
// Asm: VCVTTPD2QQ, CPU Feature: AVX512
|
||||
func (x Float64x8) ConvertToInt64() Int64x8
|
||||
|
||||
/* ConvertToUint32 */
|
||||
|
||||
// ConvertToUint32 converts element values to uint32.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result cannot be represented in uint32, an implementation-defined
|
||||
// architecture-specific value is returned.
|
||||
//
|
||||
// Asm: VCVTPS2UDQ, CPU Feature: AVX512
|
||||
// Asm: VCVTTPS2UDQ, CPU Feature: AVX512
|
||||
func (x Float32x4) ConvertToUint32() Uint32x4
|
||||
|
||||
// ConvertToUint32 converts element values to uint32.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result cannot be represented in uint32, an implementation-defined
|
||||
// architecture-specific value is returned.
|
||||
//
|
||||
// Asm: VCVTPS2UDQ, CPU Feature: AVX512
|
||||
// Asm: VCVTTPS2UDQ, CPU Feature: AVX512
|
||||
func (x Float32x8) ConvertToUint32() Uint32x8
|
||||
|
||||
// ConvertToUint32 converts element values to uint32.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result cannot be represented in uint32, an implementation-defined
|
||||
// architecture-specific value is returned.
|
||||
//
|
||||
// Asm: VCVTPS2UDQ, CPU Feature: AVX512
|
||||
// Asm: VCVTTPS2UDQ, CPU Feature: AVX512
|
||||
func (x Float32x16) ConvertToUint32() Uint32x16
|
||||
|
||||
// ConvertToUint32 converts element values to uint32.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result cannot be represented in uint32, an implementation-defined
|
||||
// architecture-specific value is returned.
|
||||
//
|
||||
// Asm: VCVTTPD2UDQX, CPU Feature: AVX512
|
||||
func (x Float64x2) ConvertToUint32() Uint32x4
|
||||
|
||||
// ConvertToUint32 converts element values to uint32.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result cannot be represented in uint32, an implementation-defined
|
||||
// architecture-specific value is returned.
|
||||
//
|
||||
// Asm: VCVTTPD2UDQY, CPU Feature: AVX512
|
||||
func (x Float64x4) ConvertToUint32() Uint32x4
|
||||
|
||||
// ConvertToUint32 converts element values to uint32.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result cannot be represented in uint32, an implementation-defined
|
||||
// architecture-specific value is returned.
|
||||
//
|
||||
// Asm: VCVTTPD2UDQ, CPU Feature: AVX512
|
||||
func (x Float64x8) ConvertToUint32() Uint32x8
|
||||
|
||||
/* ConvertToUint64 */
|
||||
|
||||
// ConvertToUint64 converts element values to uint64.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result cannot be represented in uint64, an implementation-defined
|
||||
// architecture-specific value is returned.
|
||||
//
|
||||
// Asm: VCVTTPS2UQQ, CPU Feature: AVX512
|
||||
func (x Float32x4) ConvertToUint64() Uint64x4
|
||||
|
||||
// ConvertToUint64 converts element values to uint64.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result cannot be represented in uint64, an implementation-defined
|
||||
// architecture-specific value is returned.
|
||||
//
|
||||
// Asm: VCVTTPS2UQQ, CPU Feature: AVX512
|
||||
func (x Float32x8) ConvertToUint64() Uint64x8
|
||||
|
||||
// ConvertToUint64 converts element values to uint64.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result cannot be represented in uint64, an implementation-defined
|
||||
// architecture-specific value is returned.
|
||||
//
|
||||
// Asm: VCVTTPD2UQQ, CPU Feature: AVX512
|
||||
func (x Float64x2) ConvertToUint64() Uint64x2
|
||||
|
||||
// ConvertToUint64 converts element values to uint64.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result cannot be represented in uint64, an implementation-defined
|
||||
// architecture-specific value is returned.
|
||||
//
|
||||
// Asm: VCVTTPD2UQQ, CPU Feature: AVX512
|
||||
func (x Float64x4) ConvertToUint64() Uint64x4
|
||||
|
||||
// ConvertToUint64 converts element values to uint64.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result cannot be represented in uint64, an implementation-defined
|
||||
// architecture-specific value is returned.
|
||||
//
|
||||
// Asm: VCVTTPD2UQQ, CPU Feature: AVX512
|
||||
func (x Float64x8) ConvertToUint64() Uint64x8
|
||||
|
||||
/* CopySign */
|
||||
|
||||
// CopySign returns the product of the first operand with -1, 0, or 1,
|
||||
@ -1730,152 +2022,152 @@ func (x Int8x64) DotProductQuadrupleSaturated(y Uint8x64) Int32x16
|
||||
|
||||
/* Equal */
|
||||
|
||||
// Equal compares for equality.
|
||||
// Equal returns x equals y, elementwise.
|
||||
//
|
||||
// Asm: VPCMPEQB, CPU Feature: AVX
|
||||
func (x Int8x16) Equal(y Int8x16) Mask8x16
|
||||
|
||||
// Equal compares for equality.
|
||||
// Equal returns x equals y, elementwise.
|
||||
//
|
||||
// Asm: VPCMPEQB, CPU Feature: AVX2
|
||||
func (x Int8x32) Equal(y Int8x32) Mask8x32
|
||||
|
||||
// Equal compares for equality.
|
||||
// Equal returns x equals y, elementwise.
|
||||
//
|
||||
// Asm: VPCMPEQB, CPU Feature: AVX512
|
||||
func (x Int8x64) Equal(y Int8x64) Mask8x64
|
||||
|
||||
// Equal compares for equality.
|
||||
// Equal returns x equals y, elementwise.
|
||||
//
|
||||
// Asm: VPCMPEQW, CPU Feature: AVX
|
||||
func (x Int16x8) Equal(y Int16x8) Mask16x8
|
||||
|
||||
// Equal compares for equality.
|
||||
// Equal returns x equals y, elementwise.
|
||||
//
|
||||
// Asm: VPCMPEQW, CPU Feature: AVX2
|
||||
func (x Int16x16) Equal(y Int16x16) Mask16x16
|
||||
|
||||
// Equal compares for equality.
|
||||
// Equal returns x equals y, elementwise.
|
||||
//
|
||||
// Asm: VPCMPEQW, CPU Feature: AVX512
|
||||
func (x Int16x32) Equal(y Int16x32) Mask16x32
|
||||
|
||||
// Equal compares for equality.
|
||||
// Equal returns x equals y, elementwise.
|
||||
//
|
||||
// Asm: VPCMPEQD, CPU Feature: AVX
|
||||
func (x Int32x4) Equal(y Int32x4) Mask32x4
|
||||
|
||||
// Equal compares for equality.
|
||||
// Equal returns x equals y, elementwise.
|
||||
//
|
||||
// Asm: VPCMPEQD, CPU Feature: AVX2
|
||||
func (x Int32x8) Equal(y Int32x8) Mask32x8
|
||||
|
||||
// Equal compares for equality.
|
||||
// Equal returns x equals y, elementwise.
|
||||
//
|
||||
// Asm: VPCMPEQD, CPU Feature: AVX512
|
||||
func (x Int32x16) Equal(y Int32x16) Mask32x16
|
||||
|
||||
// Equal compares for equality.
|
||||
// Equal returns x equals y, elementwise.
|
||||
//
|
||||
// Asm: VPCMPEQQ, CPU Feature: AVX
|
||||
func (x Int64x2) Equal(y Int64x2) Mask64x2
|
||||
|
||||
// Equal compares for equality.
|
||||
// Equal returns x equals y, elementwise.
|
||||
//
|
||||
// Asm: VPCMPEQQ, CPU Feature: AVX2
|
||||
func (x Int64x4) Equal(y Int64x4) Mask64x4
|
||||
|
||||
// Equal compares for equality.
|
||||
// Equal returns x equals y, elementwise.
|
||||
//
|
||||
// Asm: VPCMPEQQ, CPU Feature: AVX512
|
||||
func (x Int64x8) Equal(y Int64x8) Mask64x8
|
||||
|
||||
// Equal compares for equality.
|
||||
// Equal returns x equals y, elementwise.
|
||||
//
|
||||
// Asm: VPCMPEQB, CPU Feature: AVX
|
||||
func (x Uint8x16) Equal(y Uint8x16) Mask8x16
|
||||
|
||||
// Equal compares for equality.
|
||||
// Equal returns x equals y, elementwise.
|
||||
//
|
||||
// Asm: VPCMPEQB, CPU Feature: AVX2
|
||||
func (x Uint8x32) Equal(y Uint8x32) Mask8x32
|
||||
|
||||
// Equal compares for equality.
|
||||
// Equal returns x equals y, elementwise.
|
||||
//
|
||||
// Asm: VPCMPEQB, CPU Feature: AVX512
|
||||
func (x Uint8x64) Equal(y Uint8x64) Mask8x64
|
||||
|
||||
// Equal compares for equality.
|
||||
// Equal returns x equals y, elementwise.
|
||||
//
|
||||
// Asm: VPCMPEQW, CPU Feature: AVX
|
||||
func (x Uint16x8) Equal(y Uint16x8) Mask16x8
|
||||
|
||||
// Equal compares for equality.
|
||||
// Equal returns x equals y, elementwise.
|
||||
//
|
||||
// Asm: VPCMPEQW, CPU Feature: AVX2
|
||||
func (x Uint16x16) Equal(y Uint16x16) Mask16x16
|
||||
|
||||
// Equal compares for equality.
|
||||
// Equal returns x equals y, elementwise.
|
||||
//
|
||||
// Asm: VPCMPEQW, CPU Feature: AVX512
|
||||
func (x Uint16x32) Equal(y Uint16x32) Mask16x32
|
||||
|
||||
// Equal compares for equality.
|
||||
// Equal returns x equals y, elementwise.
|
||||
//
|
||||
// Asm: VPCMPEQD, CPU Feature: AVX
|
||||
func (x Uint32x4) Equal(y Uint32x4) Mask32x4
|
||||
|
||||
// Equal compares for equality.
|
||||
// Equal returns x equals y, elementwise.
|
||||
//
|
||||
// Asm: VPCMPEQD, CPU Feature: AVX2
|
||||
func (x Uint32x8) Equal(y Uint32x8) Mask32x8
|
||||
|
||||
// Equal compares for equality.
|
||||
// Equal returns x equals y, elementwise.
|
||||
//
|
||||
// Asm: VPCMPEQD, CPU Feature: AVX512
|
||||
func (x Uint32x16) Equal(y Uint32x16) Mask32x16
|
||||
|
||||
// Equal compares for equality.
|
||||
// Equal returns x equals y, elementwise.
|
||||
//
|
||||
// Asm: VPCMPEQQ, CPU Feature: AVX
|
||||
func (x Uint64x2) Equal(y Uint64x2) Mask64x2
|
||||
|
||||
// Equal compares for equality.
|
||||
// Equal returns x equals y, elementwise.
|
||||
//
|
||||
// Asm: VPCMPEQQ, CPU Feature: AVX2
|
||||
func (x Uint64x4) Equal(y Uint64x4) Mask64x4
|
||||
|
||||
// Equal compares for equality.
|
||||
// Equal returns x equals y, elementwise.
|
||||
//
|
||||
// Asm: VPCMPEQQ, CPU Feature: AVX512
|
||||
func (x Uint64x8) Equal(y Uint64x8) Mask64x8
|
||||
|
||||
// Equal compares for equality.
|
||||
// Equal returns x equals y, elementwise.
|
||||
//
|
||||
// Asm: VCMPPS, CPU Feature: AVX
|
||||
func (x Float32x4) Equal(y Float32x4) Mask32x4
|
||||
|
||||
// Equal compares for equality.
|
||||
// Equal returns x equals y, elementwise.
|
||||
//
|
||||
// Asm: VCMPPS, CPU Feature: AVX
|
||||
func (x Float32x8) Equal(y Float32x8) Mask32x8
|
||||
|
||||
// Equal compares for equality.
|
||||
// Equal returns x equals y, elementwise.
|
||||
//
|
||||
// Asm: VCMPPS, CPU Feature: AVX512
|
||||
func (x Float32x16) Equal(y Float32x16) Mask32x16
|
||||
|
||||
// Equal compares for equality.
|
||||
// Equal returns x equals y, elementwise.
|
||||
//
|
||||
// Asm: VCMPPD, CPU Feature: AVX
|
||||
func (x Float64x2) Equal(y Float64x2) Mask64x2
|
||||
|
||||
// Equal compares for equality.
|
||||
// Equal returns x equals y, elementwise.
|
||||
//
|
||||
// Asm: VCMPPD, CPU Feature: AVX
|
||||
func (x Float64x4) Equal(y Float64x4) Mask64x4
|
||||
|
||||
// Equal compares for equality.
|
||||
// Equal returns x equals y, elementwise.
|
||||
//
|
||||
// Asm: VCMPPD, CPU Feature: AVX512
|
||||
func (x Float64x8) Equal(y Float64x8) Mask64x8
|
||||
@ -2789,184 +3081,184 @@ func (x Uint64x8) GetLo() Uint64x4
|
||||
|
||||
/* Greater */
|
||||
|
||||
// Greater compares for greater than.
|
||||
// Greater returns x greater-than y, elementwise.
|
||||
//
|
||||
// Asm: VPCMPGTB, CPU Feature: AVX
|
||||
func (x Int8x16) Greater(y Int8x16) Mask8x16
|
||||
|
||||
// Greater compares for greater than.
|
||||
// Greater returns x greater-than y, elementwise.
|
||||
//
|
||||
// Asm: VPCMPGTB, CPU Feature: AVX2
|
||||
func (x Int8x32) Greater(y Int8x32) Mask8x32
|
||||
|
||||
// Greater compares for greater than.
|
||||
// Greater returns x greater-than y, elementwise.
|
||||
//
|
||||
// Asm: VPCMPGTB, CPU Feature: AVX512
|
||||
func (x Int8x64) Greater(y Int8x64) Mask8x64
|
||||
|
||||
// Greater compares for greater than.
|
||||
// Greater returns x greater-than y, elementwise.
|
||||
//
|
||||
// Asm: VPCMPGTW, CPU Feature: AVX
|
||||
func (x Int16x8) Greater(y Int16x8) Mask16x8
|
||||
|
||||
// Greater compares for greater than.
|
||||
// Greater returns x greater-than y, elementwise.
|
||||
//
|
||||
// Asm: VPCMPGTW, CPU Feature: AVX2
|
||||
func (x Int16x16) Greater(y Int16x16) Mask16x16
|
||||
|
||||
// Greater compares for greater than.
|
||||
// Greater returns x greater-than y, elementwise.
|
||||
//
|
||||
// Asm: VPCMPGTW, CPU Feature: AVX512
|
||||
func (x Int16x32) Greater(y Int16x32) Mask16x32
|
||||
|
||||
// Greater compares for greater than.
|
||||
// Greater returns x greater-than y, elementwise.
|
||||
//
|
||||
// Asm: VPCMPGTD, CPU Feature: AVX
|
||||
func (x Int32x4) Greater(y Int32x4) Mask32x4
|
||||
|
||||
// Greater compares for greater than.
|
||||
// Greater returns x greater-than y, elementwise.
|
||||
//
|
||||
// Asm: VPCMPGTD, CPU Feature: AVX2
|
||||
func (x Int32x8) Greater(y Int32x8) Mask32x8
|
||||
|
||||
// Greater compares for greater than.
|
||||
// Greater returns x greater-than y, elementwise.
|
||||
//
|
||||
// Asm: VPCMPGTD, CPU Feature: AVX512
|
||||
func (x Int32x16) Greater(y Int32x16) Mask32x16
|
||||
|
||||
// Greater compares for greater than.
|
||||
// Greater returns x greater-than y, elementwise.
|
||||
//
|
||||
// Asm: VPCMPGTQ, CPU Feature: AVX
|
||||
func (x Int64x2) Greater(y Int64x2) Mask64x2
|
||||
|
||||
// Greater compares for greater than.
|
||||
// Greater returns x greater-than y, elementwise.
|
||||
//
|
||||
// Asm: VPCMPGTQ, CPU Feature: AVX2
|
||||
func (x Int64x4) Greater(y Int64x4) Mask64x4
|
||||
|
||||
// Greater compares for greater than.
|
||||
// Greater returns x greater-than y, elementwise.
|
||||
//
|
||||
// Asm: VPCMPGTQ, CPU Feature: AVX512
|
||||
func (x Int64x8) Greater(y Int64x8) Mask64x8
|
||||
|
||||
// Greater compares for greater than.
|
||||
// Greater returns x greater-than y, elementwise.
|
||||
//
|
||||
// Asm: VCMPPS, CPU Feature: AVX
|
||||
func (x Float32x4) Greater(y Float32x4) Mask32x4
|
||||
|
||||
// Greater compares for greater than.
|
||||
// Greater returns x greater-than y, elementwise.
|
||||
//
|
||||
// Asm: VCMPPS, CPU Feature: AVX
|
||||
func (x Float32x8) Greater(y Float32x8) Mask32x8
|
||||
|
||||
// Greater compares for greater than.
|
||||
// Greater returns x greater-than y, elementwise.
|
||||
//
|
||||
// Asm: VCMPPS, CPU Feature: AVX512
|
||||
func (x Float32x16) Greater(y Float32x16) Mask32x16
|
||||
|
||||
// Greater compares for greater than.
|
||||
// Greater returns x greater-than y, elementwise.
|
||||
//
|
||||
// Asm: VCMPPD, CPU Feature: AVX
|
||||
func (x Float64x2) Greater(y Float64x2) Mask64x2
|
||||
|
||||
// Greater compares for greater than.
|
||||
// Greater returns x greater-than y, elementwise.
|
||||
//
|
||||
// Asm: VCMPPD, CPU Feature: AVX
|
||||
func (x Float64x4) Greater(y Float64x4) Mask64x4
|
||||
|
||||
// Greater compares for greater than.
|
||||
// Greater returns x greater-than y, elementwise.
|
||||
//
|
||||
// Asm: VCMPPD, CPU Feature: AVX512
|
||||
func (x Float64x8) Greater(y Float64x8) Mask64x8
|
||||
|
||||
// Greater compares for greater than.
|
||||
// Greater returns x greater-than y, elementwise.
|
||||
//
|
||||
// Asm: VPCMPUB, CPU Feature: AVX512
|
||||
func (x Uint8x64) Greater(y Uint8x64) Mask8x64
|
||||
|
||||
// Greater compares for greater than.
|
||||
// Greater returns x greater-than y, elementwise.
|
||||
//
|
||||
// Asm: VPCMPUW, CPU Feature: AVX512
|
||||
func (x Uint16x32) Greater(y Uint16x32) Mask16x32
|
||||
|
||||
// Greater compares for greater than.
|
||||
// Greater returns x greater-than y, elementwise.
|
||||
//
|
||||
// Asm: VPCMPUD, CPU Feature: AVX512
|
||||
func (x Uint32x16) Greater(y Uint32x16) Mask32x16
|
||||
|
||||
// Greater compares for greater than.
|
||||
// Greater returns x greater-than y, elementwise.
|
||||
//
|
||||
// Asm: VPCMPUQ, CPU Feature: AVX512
|
||||
func (x Uint64x8) Greater(y Uint64x8) Mask64x8
|
||||
|
||||
/* GreaterEqual */
|
||||
|
||||
// GreaterEqual compares for greater than or equal.
|
||||
// GreaterEqual returns x greater-than-or-equals y, elementwise.
|
||||
//
|
||||
// Asm: VCMPPS, CPU Feature: AVX
|
||||
func (x Float32x4) GreaterEqual(y Float32x4) Mask32x4
|
||||
|
||||
// GreaterEqual compares for greater than or equal.
|
||||
// GreaterEqual returns x greater-than-or-equals y, elementwise.
|
||||
//
|
||||
// Asm: VCMPPS, CPU Feature: AVX
|
||||
func (x Float32x8) GreaterEqual(y Float32x8) Mask32x8
|
||||
|
||||
// GreaterEqual compares for greater than or equal.
|
||||
// GreaterEqual returns x greater-than-or-equals y, elementwise.
|
||||
//
|
||||
// Asm: VCMPPS, CPU Feature: AVX512
|
||||
func (x Float32x16) GreaterEqual(y Float32x16) Mask32x16
|
||||
|
||||
// GreaterEqual compares for greater than or equal.
|
||||
// GreaterEqual returns x greater-than-or-equals y, elementwise.
|
||||
//
|
||||
// Asm: VCMPPD, CPU Feature: AVX
|
||||
func (x Float64x2) GreaterEqual(y Float64x2) Mask64x2
|
||||
|
||||
// GreaterEqual compares for greater than or equal.
|
||||
// GreaterEqual returns x greater-than-or-equals y, elementwise.
|
||||
//
|
||||
// Asm: VCMPPD, CPU Feature: AVX
|
||||
func (x Float64x4) GreaterEqual(y Float64x4) Mask64x4
|
||||
|
||||
// GreaterEqual compares for greater than or equal.
|
||||
// GreaterEqual returns x greater-than-or-equals y, elementwise.
|
||||
//
|
||||
// Asm: VCMPPD, CPU Feature: AVX512
|
||||
func (x Float64x8) GreaterEqual(y Float64x8) Mask64x8
|
||||
|
||||
// GreaterEqual compares for greater than or equal.
|
||||
// GreaterEqual returns x greater-than-or-equals y, elementwise.
|
||||
//
|
||||
// Asm: VPCMPB, CPU Feature: AVX512
|
||||
func (x Int8x64) GreaterEqual(y Int8x64) Mask8x64
|
||||
|
||||
// GreaterEqual compares for greater than or equal.
|
||||
// GreaterEqual returns x greater-than-or-equals y, elementwise.
|
||||
//
|
||||
// Asm: VPCMPW, CPU Feature: AVX512
|
||||
func (x Int16x32) GreaterEqual(y Int16x32) Mask16x32
|
||||
|
||||
// GreaterEqual compares for greater than or equal.
|
||||
// GreaterEqual returns x greater-than-or-equals y, elementwise.
|
||||
//
|
||||
// Asm: VPCMPD, CPU Feature: AVX512
|
||||
func (x Int32x16) GreaterEqual(y Int32x16) Mask32x16
|
||||
|
||||
// GreaterEqual compares for greater than or equal.
|
||||
// GreaterEqual returns x greater-than-or-equals y, elementwise.
|
||||
//
|
||||
// Asm: VPCMPQ, CPU Feature: AVX512
|
||||
func (x Int64x8) GreaterEqual(y Int64x8) Mask64x8
|
||||
|
||||
// GreaterEqual compares for greater than or equal.
|
||||
// GreaterEqual returns x greater-than-or-equals y, elementwise.
|
||||
//
|
||||
// Asm: VPCMPUB, CPU Feature: AVX512
|
||||
func (x Uint8x64) GreaterEqual(y Uint8x64) Mask8x64
|
||||
|
||||
// GreaterEqual compares for greater than or equal.
|
||||
// GreaterEqual returns x greater-than-or-equals y, elementwise.
|
||||
//
|
||||
// Asm: VPCMPUW, CPU Feature: AVX512
|
||||
func (x Uint16x32) GreaterEqual(y Uint16x32) Mask16x32
|
||||
|
||||
// GreaterEqual compares for greater than or equal.
|
||||
// GreaterEqual returns x greater-than-or-equals y, elementwise.
|
||||
//
|
||||
// Asm: VPCMPUD, CPU Feature: AVX512
|
||||
func (x Uint32x16) GreaterEqual(y Uint32x16) Mask32x16
|
||||
|
||||
// GreaterEqual compares for greater than or equal.
|
||||
// GreaterEqual returns x greater-than-or-equals y, elementwise.
|
||||
//
|
||||
// Asm: VPCMPUQ, CPU Feature: AVX512
|
||||
func (x Uint64x8) GreaterEqual(y Uint64x8) Mask64x8
|
||||
@ -3255,144 +3547,144 @@ func (x Uint64x8) LeadingZeros() Uint64x8
|
||||
|
||||
/* Less */
|
||||
|
||||
// Less compares for less than.
|
||||
// Less returns x less-than y, elementwise.
|
||||
//
|
||||
// Asm: VCMPPS, CPU Feature: AVX
|
||||
func (x Float32x4) Less(y Float32x4) Mask32x4
|
||||
|
||||
// Less compares for less than.
|
||||
// Less returns x less-than y, elementwise.
|
||||
//
|
||||
// Asm: VCMPPS, CPU Feature: AVX
|
||||
func (x Float32x8) Less(y Float32x8) Mask32x8
|
||||
|
||||
// Less compares for less than.
|
||||
// Less returns x less-than y, elementwise.
|
||||
//
|
||||
// Asm: VCMPPS, CPU Feature: AVX512
|
||||
func (x Float32x16) Less(y Float32x16) Mask32x16
|
||||
|
||||
// Less compares for less than.
|
||||
// Less returns x less-than y, elementwise.
|
||||
//
|
||||
// Asm: VCMPPD, CPU Feature: AVX
|
||||
func (x Float64x2) Less(y Float64x2) Mask64x2
|
||||
|
||||
// Less compares for less than.
|
||||
// Less returns x less-than y, elementwise.
|
||||
//
|
||||
// Asm: VCMPPD, CPU Feature: AVX
|
||||
func (x Float64x4) Less(y Float64x4) Mask64x4
|
||||
|
||||
// Less compares for less than.
|
||||
// Less returns x less-than y, elementwise.
|
||||
//
|
||||
// Asm: VCMPPD, CPU Feature: AVX512
|
||||
func (x Float64x8) Less(y Float64x8) Mask64x8
|
||||
|
||||
// Less compares for less than.
|
||||
// Less returns x less-than y, elementwise.
|
||||
//
|
||||
// Asm: VPCMPB, CPU Feature: AVX512
|
||||
func (x Int8x64) Less(y Int8x64) Mask8x64
|
||||
|
||||
// Less compares for less than.
|
||||
// Less returns x less-than y, elementwise.
|
||||
//
|
||||
// Asm: VPCMPW, CPU Feature: AVX512
|
||||
func (x Int16x32) Less(y Int16x32) Mask16x32
|
||||
|
||||
// Less compares for less than.
|
||||
// Less returns x less-than y, elementwise.
|
||||
//
|
||||
// Asm: VPCMPD, CPU Feature: AVX512
|
||||
func (x Int32x16) Less(y Int32x16) Mask32x16
|
||||
|
||||
// Less compares for less than.
|
||||
// Less returns x less-than y, elementwise.
|
||||
//
|
||||
// Asm: VPCMPQ, CPU Feature: AVX512
|
||||
func (x Int64x8) Less(y Int64x8) Mask64x8
|
||||
|
||||
// Less compares for less than.
|
||||
// Less returns x less-than y, elementwise.
|
||||
//
|
||||
// Asm: VPCMPUB, CPU Feature: AVX512
|
||||
func (x Uint8x64) Less(y Uint8x64) Mask8x64
|
||||
|
||||
// Less compares for less than.
|
||||
// Less returns x less-than y, elementwise.
|
||||
//
|
||||
// Asm: VPCMPUW, CPU Feature: AVX512
|
||||
func (x Uint16x32) Less(y Uint16x32) Mask16x32
|
||||
|
||||
// Less compares for less than.
|
||||
// Less returns x less-than y, elementwise.
|
||||
//
|
||||
// Asm: VPCMPUD, CPU Feature: AVX512
|
||||
func (x Uint32x16) Less(y Uint32x16) Mask32x16
|
||||
|
||||
// Less compares for less than.
|
||||
// Less returns x less-than y, elementwise.
|
||||
//
|
||||
// Asm: VPCMPUQ, CPU Feature: AVX512
|
||||
func (x Uint64x8) Less(y Uint64x8) Mask64x8
|
||||
|
||||
/* LessEqual */
|
||||
|
||||
// LessEqual compares for less than or equal.
|
||||
// LessEqual returns x less-than-or-equals y, elementwise.
|
||||
//
|
||||
// Asm: VCMPPS, CPU Feature: AVX
|
||||
func (x Float32x4) LessEqual(y Float32x4) Mask32x4
|
||||
|
||||
// LessEqual compares for less than or equal.
|
||||
// LessEqual returns x less-than-or-equals y, elementwise.
|
||||
//
|
||||
// Asm: VCMPPS, CPU Feature: AVX
|
||||
func (x Float32x8) LessEqual(y Float32x8) Mask32x8
|
||||
|
||||
// LessEqual compares for less than or equal.
|
||||
// LessEqual returns x less-than-or-equals y, elementwise.
|
||||
//
|
||||
// Asm: VCMPPS, CPU Feature: AVX512
|
||||
func (x Float32x16) LessEqual(y Float32x16) Mask32x16
|
||||
|
||||
// LessEqual compares for less than or equal.
|
||||
// LessEqual returns x less-than-or-equals y, elementwise.
|
||||
//
|
||||
// Asm: VCMPPD, CPU Feature: AVX
|
||||
func (x Float64x2) LessEqual(y Float64x2) Mask64x2
|
||||
|
||||
// LessEqual compares for less than or equal.
|
||||
// LessEqual returns x less-than-or-equals y, elementwise.
|
||||
//
|
||||
// Asm: VCMPPD, CPU Feature: AVX
|
||||
func (x Float64x4) LessEqual(y Float64x4) Mask64x4
|
||||
|
||||
// LessEqual compares for less than or equal.
|
||||
// LessEqual returns x less-than-or-equals y, elementwise.
|
||||
//
|
||||
// Asm: VCMPPD, CPU Feature: AVX512
|
||||
func (x Float64x8) LessEqual(y Float64x8) Mask64x8
|
||||
|
||||
// LessEqual compares for less than or equal.
|
||||
// LessEqual returns x less-than-or-equals y, elementwise.
|
||||
//
|
||||
// Asm: VPCMPB, CPU Feature: AVX512
|
||||
func (x Int8x64) LessEqual(y Int8x64) Mask8x64
|
||||
|
||||
// LessEqual compares for less than or equal.
|
||||
// LessEqual returns x less-than-or-equals y, elementwise.
|
||||
//
|
||||
// Asm: VPCMPW, CPU Feature: AVX512
|
||||
func (x Int16x32) LessEqual(y Int16x32) Mask16x32
|
||||
|
||||
// LessEqual compares for less than or equal.
|
||||
// LessEqual returns x less-than-or-equals y, elementwise.
|
||||
//
|
||||
// Asm: VPCMPD, CPU Feature: AVX512
|
||||
func (x Int32x16) LessEqual(y Int32x16) Mask32x16
|
||||
|
||||
// LessEqual compares for less than or equal.
|
||||
// LessEqual returns x less-than-or-equals y, elementwise.
|
||||
//
|
||||
// Asm: VPCMPQ, CPU Feature: AVX512
|
||||
func (x Int64x8) LessEqual(y Int64x8) Mask64x8
|
||||
|
||||
// LessEqual compares for less than or equal.
|
||||
// LessEqual returns x less-than-or-equals y, elementwise.
|
||||
//
|
||||
// Asm: VPCMPUB, CPU Feature: AVX512
|
||||
func (x Uint8x64) LessEqual(y Uint8x64) Mask8x64
|
||||
|
||||
// LessEqual compares for less than or equal.
|
||||
// LessEqual returns x less-than-or-equals y, elementwise.
|
||||
//
|
||||
// Asm: VPCMPUW, CPU Feature: AVX512
|
||||
func (x Uint16x32) LessEqual(y Uint16x32) Mask16x32
|
||||
|
||||
// LessEqual compares for less than or equal.
|
||||
// LessEqual returns x less-than-or-equals y, elementwise.
|
||||
//
|
||||
// Asm: VPCMPUD, CPU Feature: AVX512
|
||||
func (x Uint32x16) LessEqual(y Uint32x16) Mask32x16
|
||||
|
||||
// LessEqual compares for less than or equal.
|
||||
// LessEqual returns x less-than-or-equals y, elementwise.
|
||||
//
|
||||
// Asm: VPCMPUQ, CPU Feature: AVX512
|
||||
func (x Uint64x8) LessEqual(y Uint64x8) Mask64x8
|
||||
@ -3979,72 +4271,72 @@ func (x Float64x8) MulSubAdd(y Float64x8, z Float64x8) Float64x8
|
||||
|
||||
/* NotEqual */
|
||||
|
||||
// NotEqual compares for inequality.
|
||||
// NotEqual returns x not-equals y, elementwise.
|
||||
//
|
||||
// Asm: VCMPPS, CPU Feature: AVX
|
||||
func (x Float32x4) NotEqual(y Float32x4) Mask32x4
|
||||
|
||||
// NotEqual compares for inequality.
|
||||
// NotEqual returns x not-equals y, elementwise.
|
||||
//
|
||||
// Asm: VCMPPS, CPU Feature: AVX
|
||||
func (x Float32x8) NotEqual(y Float32x8) Mask32x8
|
||||
|
||||
// NotEqual compares for inequality.
|
||||
// NotEqual returns x not-equals y, elementwise.
|
||||
//
|
||||
// Asm: VCMPPS, CPU Feature: AVX512
|
||||
func (x Float32x16) NotEqual(y Float32x16) Mask32x16
|
||||
|
||||
// NotEqual compares for inequality.
|
||||
// NotEqual returns x not-equals y, elementwise.
|
||||
//
|
||||
// Asm: VCMPPD, CPU Feature: AVX
|
||||
func (x Float64x2) NotEqual(y Float64x2) Mask64x2
|
||||
|
||||
// NotEqual compares for inequality.
|
||||
// NotEqual returns x not-equals y, elementwise.
|
||||
//
|
||||
// Asm: VCMPPD, CPU Feature: AVX
|
||||
func (x Float64x4) NotEqual(y Float64x4) Mask64x4
|
||||
|
||||
// NotEqual compares for inequality.
|
||||
// NotEqual returns x not-equals y, elementwise.
|
||||
//
|
||||
// Asm: VCMPPD, CPU Feature: AVX512
|
||||
func (x Float64x8) NotEqual(y Float64x8) Mask64x8
|
||||
|
||||
// NotEqual compares for inequality.
|
||||
// NotEqual returns x not-equals y, elementwise.
|
||||
//
|
||||
// Asm: VPCMPB, CPU Feature: AVX512
|
||||
func (x Int8x64) NotEqual(y Int8x64) Mask8x64
|
||||
|
||||
// NotEqual compares for inequality.
|
||||
// NotEqual returns x not-equals y, elementwise.
|
||||
//
|
||||
// Asm: VPCMPW, CPU Feature: AVX512
|
||||
func (x Int16x32) NotEqual(y Int16x32) Mask16x32
|
||||
|
||||
// NotEqual compares for inequality.
|
||||
// NotEqual returns x not-equals y, elementwise.
|
||||
//
|
||||
// Asm: VPCMPD, CPU Feature: AVX512
|
||||
func (x Int32x16) NotEqual(y Int32x16) Mask32x16
|
||||
|
||||
// NotEqual compares for inequality.
|
||||
// NotEqual returns x not-equals y, elementwise.
|
||||
//
|
||||
// Asm: VPCMPQ, CPU Feature: AVX512
|
||||
func (x Int64x8) NotEqual(y Int64x8) Mask64x8
|
||||
|
||||
// NotEqual compares for inequality.
|
||||
// NotEqual returns x not-equals y, elementwise.
|
||||
//
|
||||
// Asm: VPCMPUB, CPU Feature: AVX512
|
||||
func (x Uint8x64) NotEqual(y Uint8x64) Mask8x64
|
||||
|
||||
// NotEqual compares for inequality.
|
||||
// NotEqual returns x not-equals y, elementwise.
|
||||
//
|
||||
// Asm: VPCMPUW, CPU Feature: AVX512
|
||||
func (x Uint16x32) NotEqual(y Uint16x32) Mask16x32
|
||||
|
||||
// NotEqual compares for inequality.
|
||||
// NotEqual returns x not-equals y, elementwise.
|
||||
//
|
||||
// Asm: VPCMPUD, CPU Feature: AVX512
|
||||
func (x Uint32x16) NotEqual(y Uint32x16) Mask32x16
|
||||
|
||||
// NotEqual compares for inequality.
|
||||
// NotEqual returns x not-equals y, elementwise.
|
||||
//
|
||||
// Asm: VPCMPUQ, CPU Feature: AVX512
|
||||
func (x Uint64x8) NotEqual(y Uint64x8) Mask64x8
|
||||
|
||||
Loading…
Reference in New Issue
Block a user